Charagulla; Sanjay K.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Charagulla; Sanjay K..The latest application filed is for "memory interface circuitry with phase detection".
- Charagulla; Sanjay K. - San Jose CA
| Patent | Date |
|---|---|
| Techniques for providing adjustable on-chip termination impedance Grant 7,825,682 - Wang , et al. November 2, 2 | 2010-11-02 |
| Memory interface circuitry with phase detection Grant 7,664,978 - Burney , et al. February 16, 2 | 2010-02-16 |
| Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry Grant 7,555,667 - Burney , et al. June 30, 2 | 2009-06-30 |
| Fully buffered DIMM system and method with hard-IP memory controller and soft-IP frequency controller Grant 7,490,209 - Charagulla February 10, 2 | 2009-02-10 |
| Techniques for providing adjustable on-chip termination impedance Grant 7,417,452 - Wang , et al. August 26, 2 | 2008-08-26 |
| Modular I/O bank architecture Grant 7,378,868 - Tyhach , et al. May 27, 2 | 2008-05-27 |
| DQS postamble filtering Grant 7,324,405 - Charagulla , et al. January 29, 2 | 2008-01-29 |
| Enhanced DLL phase output scheme Grant 7,282,973 - Charagulla , et al. October 16, 2 | 2007-10-16 |
| Memory interface circuitry with phase detection App 20070240012 - Burney; Ali ; et al. | 2007-10-11 |
| Modular I/o Bank Architecture App 20070165478 - Tyhach; Jeffrey ; et al. | 2007-07-19 |
| DQS postamble filtering Grant 7,031,222 - Charagulla , et al. April 18, 2 | 2006-04-18 |
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