loadpatents
name:-0.0045280456542969
name:-0.013345003128052
name:-0.0018069744110107
CHAPPELL; Barbara A. Patent Filings

CHAPPELL; Barbara A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHAPPELL; Barbara A..The latest application filed is for "multi version library cell handling and integrated circuit structures fabricated therefrom".

Company Profile
1.13.6
  • CHAPPELL; Barbara A. - Portland OR
  • Chappell; Barbara A. - Hillsboro OR US
  • Chappell; Barbara A. - Amawalk NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Multi Version Library Cell Handling And Integrated Circuit Structures Fabricated Therefrom
App 20220149075 - KUMAR; Ranjith ;   et al.
2022-05-12
Multi version library cell handling and integrated circuit structures fabricated therefrom
Grant 11,271,010 - Kumar , et al. March 8, 2
2022-03-08
Through Gate Fin Isolation
App 20210233908 - BOHR; Mark T. ;   et al.
2021-07-29
Through gate fin isolation
Grant 11,037,923 - Bohr , et al. June 15, 2
2021-06-15
Multi Version Library Cell Handling And Integrated Circuit Structures Fabricated Therefrom
App 20200357823 - KUMAR; Ranjith ;   et al.
2020-11-12
Through Gate Fin Isolation
App 20140001572 - BOHR; Mark T. ;   et al.
2014-01-02
VDD modulated SRAM for highly scaled, high performance cache
Grant 6,556,471 - Chappell , et al. April 29, 2
2003-04-29
VDD modulated sram for highly scaled, high performance cache
App 20030012048 - Chappell, Barbara A. ;   et al.
2003-01-16
High speed ratioed CMOS logic structures for a pulsed input environment
Grant 5,942,917 - Chappell , et al. August 24, 1
1999-08-24
Virtual multi-port RAM employing multiple accesses during single machine cycle
Grant 5,542,067 - Chappell , et al. July 30, 1
1996-07-30
Virtual multi-port RAM
Grant 5,204,841 - Chappell , et al. April 20, 1
1993-04-20
Transporsable memory architecture
Grant 4,845,669 - Chappell , et al. July 4, 1
1989-07-04
Pipelined memory chip structure having improved cycle time
Grant 4,845,677 - Chappell , et al. July 4, 1
1989-07-04
Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories
Grant 4,843,261 - Chappell , et al. June 27, 1
1989-06-27
Multi-stage pass transistor shifter/rotator
Grant 4,583,197 - Chappell , et al. April 15, 1
1986-04-15
High performance FET driver circuit
Grant 4,491,748 - Chappell , et al. January 1, 1
1985-01-01
Heterojunction semiconductor
Grant 4,460,910 - Chappell , et al. July 17, 1
1984-07-17

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