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name:-0.0053169727325439
name:-0.0064880847930908
name:-0.0012521743774414
Chapman; Phillip Francis Patent Filings

Chapman; Phillip Francis

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chapman; Phillip Francis.The latest application filed is for "bias-controlled deep trench substrate noise isolation integrated circuit device structures".

Company Profile
0.5.5
  • Chapman; Phillip Francis - Essex Junction VT
  • Chapman; Phillip Francis - Colchester VT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Bias-controlled Deep Trench Substrate Noise Isolation Integrated Circuit Device Structures
App 20110291238 - Chapman; Phillip Francis ;   et al.
2011-12-01
Bias-controlled deep trench substrate noise isolation integrated circuit device structures
Grant 8,021,941 - Chapman , et al. September 20, 2
2011-09-20
Bias-controlled Deep Trench Substrate Noise Isolation Integrated Circuit Device Structures
App 20110018094 - Chapman; Phillip Francis ;   et al.
2011-01-27
Structure for a latchup robust array I/O using through wafer via
Grant 7,855,420 - Chapman , et al. December 21, 2
2010-12-21
Latchup robust array I/O using through wafer via
Grant 7,741,681 - Chapman , et al. June 22, 2
2010-06-22
Structure for a latchup robust gate array using through wafer via
Grant 7,696,541 - Chapman , et al. April 13, 2
2010-04-13
Structure For A Latchup Robust Array I/o Using Through Wafer Via
App 20090152592 - Chapman; Phillip Francis ;   et al.
2009-06-18
Structure For A Latchup Robust Gate Array Using Through Wafer Via
App 20090152593 - Chapman; Phillip Francis ;   et al.
2009-06-18
Latchup Robust Array I/o Using Through Wafer Via
App 20090152632 - Chapman; Phillip Francis ;   et al.
2009-06-18
Latchup robust gate array using through wafer via
Grant 7,498,622 - Chapman , et al. March 3, 2
2009-03-03

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