| Patent | Date |
|---|
Configuration and fabrication of semiconductor structure using empty and filled wells
Grant 8,735,980 - Bulucea , et al. May 27, 2 | 2014-05-27 |
Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile
Grant 8,673,720 - Chaparala , et al. March 18, 2 | 2014-03-18 |
Configuration And Fabrication Of Semiconductor Structure Using Empty And Filled Wells
App 20130126970 - Bulucea; Constantin ; et al. | 2013-05-23 |
Configuration and fabrication of semiconductor structure using empty and filled wells
Grant 8,304,835 - Bulucea , et al. November 6, 2 | 2012-11-06 |
Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction Capacitance
App 20120273880 - Teng; Chih Sieh ; et al. | 2012-11-01 |
Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile
Grant 8,253,208 - Chaparala , et al. August 28, 2 | 2012-08-28 |
Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction Capacitance
App 20120181620 - Bulucea; Constantin ; et al. | 2012-07-19 |
Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction Capacitance
App 20120181614 - Teng; Chih Sieh ; et al. | 2012-07-19 |
Fabrication of field-effect transistor with vertical body-material dopant profile tailored to alleviate punchthrough and reduce current leakage
Grant 8,129,262 - Bulucea , et al. March 6, 2 | 2012-03-06 |
Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length
Grant 7,879,669 - Teng , et al. February 1, 2 | 2011-02-01 |
Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile
App 20100244148 - Chaparala; Prasad ; et al. | 2010-09-30 |
Configuration and fabrication of semiconductor structure using empty and filled wells
App 20100244128 - Bulucea; Constantin ; et al. | 2010-09-30 |
Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage
Grant 7,785,971 - Bulucea , et al. August 31, 2 | 2010-08-31 |
Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays
Grant 7,718,448 - Brisbin , et al. May 18, 2 | 2010-05-18 |
Structure and fabrication of field-effect transistor for alleviating short-channel effects
Grant 7,700,980 - Bulucea , et al. April 20, 2 | 2010-04-20 |
Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics
Grant 7,701,005 - Bulucea , et al. April 20, 2 | 2010-04-20 |
MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation
Grant 7,645,657 - Brisbin , et al. January 12, 2 | 2010-01-12 |
Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics
Grant 7,595,244 - Bulucea , et al. September 29, 2 | 2009-09-29 |
MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation
App 20090146192 - Brisbin; Douglas ; et al. | 2009-06-11 |
Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level
Grant 7,390,682 - Chaparala , et al. June 24, 2 | 2008-06-24 |
Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level
App 20070051951 - Chaparala; Prasad ; et al. | 2007-03-08 |
Method and structure for testing metal-insulator-metal capacitor structures under high temperature at wafer level
Grant 7,170,090 - Chaparala , et al. January 30, 2 | 2007-01-30 |
P-channel field-effect transistor with reduced junction capacitance
Grant 7,145,191 - Teng , et al. December 5, 2 | 2006-12-05 |
Method of programming an antifuse
Grant 6,927,474 - O'Connell , et al. August 9, 2 | 2005-08-09 |
Fabrication of p-channel field-effect transistor for reducing junction capacitance
Grant 6,797,576 - Teng , et al. September 28, 2 | 2004-09-28 |
Direct implantation of fluorine into the channel region of a PMOS device
Grant 6,797,555 - Hopper , et al. September 28, 2 | 2004-09-28 |
Fabrication of field-effect transistor for alleviating short-channel effects
Grant 6,599,804 - Bulucea , et al. July 29, 2 | 2003-07-29 |
Field-effect transistor for alleviating short-channel effects
Grant 6,548,842 - Bulucea , et al. April 15, 2 | 2003-04-15 |
Fabrication of field-effect transistor for alleviating short-channel effects and/or reducing junction capacitance
App 20020074612 - Bulucea, Constantin ; et al. | 2002-06-20 |
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