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Chao; Yuan-Ju Patent Filings

Chao; Yuan-Ju

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chao; Yuan-Ju.The latest application filed is for "method of data conversion for computing-in-memory".

Company Profile
8.37.14
  • Chao; Yuan-Ju - Cupertino CA
  • Chao; Yuan-Ju - Santa Clara CA US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method Of Data Conversion For Computing-in-memory
App 20220158651 - Chao; Yuan-Ju
2022-05-19
SAR ADC using value shifted capacitive DAC for improved reference settling and higher conversion rate
Grant 11,245,412 - Chao February 8, 2
2022-02-08
Digital corrected two-step SAR ADC
Grant 10,938,399 - Chao , et al. March 2, 2
2021-03-02
On-chip pattern generator for high speed digital-to-analog converter
Grant 10,873,339 - Chao December 22, 2
2020-12-22
Method of capacitive DAC calibration for SAR ADC
Grant 10,715,163 - Chao
2020-07-14
Method Of Capacitive Dac Calibration For Sar Adc
App 20200195266 - CHAO; YUAN-JU
2020-06-18
Programmable gain amplifier (PGA) embedded pipelined analog to digital converters (ADC) for wide input full scale range
Grant 10,686,459 - Chao
2020-06-16
Process, Voltage And Temperature Optimized Asynchronous Sar Adc
App 20200169263 - CHAO; YUAN-JU
2020-05-28
Process, voltage and temperature optimized asynchronous SAR ADC
Grant 10,644,713 - Chao
2020-05-05
Sar Adc Using Value Shifted Capacitive Dac For Improved Reference Settling And Higher Conversion Rate
App 20200119745 - CHAO; Yuan-Ju
2020-04-16
Programmable Gain Apmplifier (pga) Embedded Pipelined Analog To Digital Converters (adc) For Wide Input Full Scale Range
App 20200014393 - CHAO; YUAN-JU
2020-01-09
Method of capacitive DAC calibration for SAR ADC
Grant 10,523,228 - Chao Dec
2019-12-31
Process, voltage and temperature optimized asynchronous SAR ADC
Grant 10,505,559 - Chao Dec
2019-12-10
System and method for anti reverse engineering for analog integrated circuit
Grant 10,460,061 - Chao , et al. Oc
2019-10-29
System And Method For Anti Reverse Engineering For Analog Integrated Circuit
App 20190102502 - CHAO; YUAN-JU ;   et al.
2019-04-04
High Speed Sar Adc Using Comparator Output Triggered Binary-search Timing Scheme And Bit-dependent Dac Settling
App 20180331689 - CHAO; YUAN-JU ;   et al.
2018-11-15
High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling
Grant 10,128,860 - Chao , et al. November 13, 2
2018-11-13
System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC
Grant 10,014,874 - Chao , et al. July 3, 2
2018-07-03
Programmable duty-cycle low jitter differential clock buffer
Grant 9,979,382 - Chao , et al. May 22, 2
2018-05-22
Appapatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters
Grant 9,866,236 - Chao , et al. January 9, 2
2018-01-09
System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC
Grant 9,843,336 - Chao , et al. December 12, 2
2017-12-12
Apparatus and method of self-healing data converters
Grant 9,813,075 - Chao November 7, 2
2017-11-07
High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling
Grant 9,774,337 - Chao , et al. September 26, 2
2017-09-26
Apparatus and method of self-healing data converters
Grant 9,667,263 - Chao May 30, 2
2017-05-30
Apparatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters
Grant 9,621,180 - Chao , et al. April 11, 2
2017-04-11
Precision half cell for sub-FEMTO unit cap and capacitive DAC architecture in SAR ADC
Grant 9,418,788 - Srinivas , et al. August 16, 2
2016-08-16
Precision Half Cell For Sub-femto Unit Cap And Capacitive Dac Architecture In Sar Adc
App 20150263754 - Srinivas; Vijay ;   et al.
2015-09-17
Tree structured supply and bias distribution layout
Grant 8,610,612 - Keramat , et al. December 17, 2
2013-12-17
Data converter current sources using thin-oxide core devices
Grant 8,537,040 - Keramat , et al. September 17, 2
2013-09-17
Tree Structured Supply And Bias Distribution Layout
App 20130222167 - Keramat; Mansour ;   et al.
2013-08-29
Data Converter Current Sources Using Thin-oxide Core Devices
App 20130120177 - Keramat; Mansour ;   et al.
2013-05-16
System and method for modifying output power of an information communication system
Grant 7,808,322 - Son , et al. October 5, 2
2010-10-05
Dual reference current generation using a single external reference resistor
Grant 7,733,076 - Shirvani-Mahdavi , et al. June 8, 2
2010-06-08
System and method for modifying output power of an information communication system
Grant 7,167,045 - Son , et al. January 23, 2
2007-01-23

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