loadpatents
name:-0.0089709758758545
name:-0.0064630508422852
name:-0.0004889965057373
Chao; Tze-hsiang Patent Filings

Chao; Tze-hsiang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chao; Tze-hsiang.The latest application filed is for "conductive structure for electronic device".

Company Profile
0.6.7
  • Chao; Tze-hsiang - Hsinchu TW
  • Chao; Tze-Hsiang - Hsin Chu City TW
  • Chao; Tze-hsiang - Hsinchu City TW
  • Chao; Tze-Hsiang - Hsin-Chu TW
  • Chao, Tze-Hsiang - San-Ming District TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
System and method for clock switching
Grant 7,411,429 - Yang , et al. August 12, 2
2008-08-12
Conductive structure for electronic device
App 20070241456 - Chao; Tze-Hsiang ;   et al.
2007-10-18
System and method for clock switching
App 20070096774 - Yang; Chia-hao ;   et al.
2007-05-03
Apparatus And Method Of Controlling And Tuning A Fine Calibration For Clock Source Synchronization In Dual Loop Of Hybrid Phase And Time Domain
App 20070090862 - Chao; Tze-hsiang ;   et al.
2007-04-26
Tile-based routing method of a multi-layer circuit board and related structure
Grant 7,208,403 - Fang , et al. April 24, 2
2007-04-24
Apparatus and method of controlling and tuning a fine calibration for clock source synchronization in dual loop of hybrid phase and time domain
Grant 7,202,716 - Chao , et al. April 10, 2
2007-04-10
Apparatus and method of controlling clock phase alignment with dual loop of hybrid phase and time domain for clock source synchronization
Grant 7,183,821 - Chao , et al. February 27, 2
2007-02-27
Tile-based Routing Method Of A Multi-layer Circuit Board And Related Structure
App 20060154402 - Fang; Chung-Yi ;   et al.
2006-07-13
Tile-based routing method of a multi-layer circuit board
Grant 7,043,828 - Fang , et al. May 16, 2
2006-05-16
Multi-stage delay clock generator
Grant 7,034,589 - Chao April 25, 2
2006-04-25
A Multi-stage Delay Clock Generator
App 20050189974 - Chao, Tze-Hsiang
2005-09-01
Tile-based Routing Method Of A Multi-layer Circuit Board And Related Structure
App 20040255457 - Fang, Chung-Yi ;   et al.
2004-12-23
Quasi-synchronous multi-stage event synchronization apparatus
App 20040057548 - Su, Jen-Pin ;   et al.
2004-03-25

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed