loadpatents
name:-0.0028688907623291
name:-0.016600847244263
name:-0.00044393539428711
Chao; Li-Chih Patent Filings

Chao; Li-Chih

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chao; Li-Chih.The latest application filed is for "dual damascene process".

Company Profile
0.13.2
  • Chao; Li-Chih - Tao-Yuan TW
  • Chao; Li-Chih - Yan-mei TW
  • Chao; Li-Chih - Yang-mei TW
  • Chao; Li-chih - Fang-mei TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Dual damascene process
Grant 7,253,112 - Ho , et al. August 7, 2
2007-08-07
Dual damascene process
App 20050014362 - Ho, Bang-Chien ;   et al.
2005-01-20
Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach
Grant 6,797,630 - Wu , et al. September 28, 2
2004-09-28
Organic low K dielectric etch with NH3 chemistry
Grant 6,743,732 - Lin , et al. June 1, 2
2004-06-01
Prevention of spiking in ultra low dielectric constant material
Grant 6,727,183 - Ma , et al. April 27, 2
2004-04-27
Method of dual damascene patterning
Grant 6,720,256 - Wu , et al. April 13, 2
2004-04-13
Method for improved plasma etching control
App 20030155329 - Su, Yi-Nien ;   et al.
2003-08-21
N2/H2 chemistry for dry development in top surface imaging technology
Grant 6,551,938 - Wu , et al. April 22, 2
2003-04-22
Method of cleaning a copper/porous low-k dual damascene etch
Grant 6,457,477 - Young , et al. October 1, 2
2002-10-01
Partial hard mask open process for hard mask dual damascene etch
Grant 6,376,366 - Lin , et al. April 23, 2
2002-04-23
Fully dry post-via-etch cleaning method for a damascene process
Grant 6,323,121 - Liu , et al. November 27, 2
2001-11-27
Dual damascene process for carbon-based low-K materials
Grant 6,211,061 - Chen , et al. April 3, 2
2001-04-03
Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
Grant 6,165,880 - Yaung , et al. December 26, 2
2000-12-26
Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation
Grant 6,140,218 - Liu , et al. October 31, 2
2000-10-31
Self-aligned contact structures using high selectivity etching
Grant 5,872,063 - Chao , et al. February 16, 1
1999-02-16

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