CHAO; Hsin-Lung

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHAO; Hsin-Lung.The latest application filed is for "multi-depth etching in semiconductor arrangement".

Company Profile

5.4.6

CHAO; Hsin-Lung - Hsinchu City TW
Chao; Hsin-Lung - Hsinchu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-depth Etching In Semiconductor Arrangement App 20210066132 - CHIANG; Tsung-Yu ; et al.	2021-03-04
Methods for forming a semiconductor arrangement of fins having multiple heights and an alignment mark Grant 10,840,143 - Chiang , et al. November 17, 2	2020-11-17
Multi-depth Etching In Semiconductor Arrangement App 20190096766 - CHIANG; Tsung-Yu ; et al.	2019-03-28
Semiconductor arrangement with fins having multiple heights and a dielectric layer recessed in the substrate Grant 10,177,036 - Chiang , et al. J	2019-01-08
Multi-depth Etching In Semiconductor Arrangement App 20180174914 - Chiang; Tsung-Yu ; et al.	2018-06-21
Methods for forming a semiconductor arrangement with multiple-height fins and substrate trenches Grant 9,911,658 - Chiang , et al. March 6, 2	2018-03-06
Multi-depth Etching In Semiconductor Arrangement App 20170084494 - Chiang; Tsung-Yu ; et al.	2017-03-23
Semiconductor arrangement with multiple-height fins and substrate trenches Grant 9,515,184 - Chiang , et al. December 6, 2	2016-12-06
Multi-depth Etching In Semiconductor Arrangement App 20150069528 - Chiang; Tsung-Yu ; et al.	2015-03-12

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