Chang; Young Uk

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Young Uk.The latest application filed is for "chip-on-film package and semiconductor chip".

Company Profile

2.13.13

Chang; Young Uk - Daejeon KR
Chang; Young-Uk - Suwon-si KR
Chang; Young-Uk - Gyeonggi-do KR
Chang; Young-uk - Kyounggi-do KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Chip-On-Film Package and Semiconductor Chip App 20220199512 - Chang; Young Uk	2022-06-23
Driving system for a double rate driving display Grant 11,222,571 - Jeong , et al. January 11, 2	2022-01-11
Driving apparatus for double rate driving display Grant 11,222,572 - Jeong , et al. January 11, 2	2022-01-11
Driving Apparatus For Display App 20210183292 - Jeong; Hyun Woo ; et al.	2021-06-17
System For Display App 20210183291 - Jeong; Hyun Woo ; et al.	2021-06-17
Display device and driver thereof Grant 10,747,360 - Park , et al. A	2020-08-18
Display Device And Driver Thereof App 20190339808 - PARK; Jong Min ; et al.	2019-11-07
Memory device, memory system and method of verifying repair result of memory device Grant 10,115,479 - Kim , et al. October 30, 2	2018-10-30
Memory Device, Memory System And Method Of Verifying Repair Result Of Memory Device App 20170148529 - KIM; Seok-Jung ; et al.	2017-05-25
Semiconductor memory device for controlling operation of delay-locked loop circuit Grant 8,730,751 - Kim , et al. May 20, 2	2014-05-20
Semiconductor Memory Device For Controlling Operation Of Delay-locked Loop Circuit App 20120218848 - KIM; JUN-BAE ; et al.	2012-08-30
Semiconductor memory device for controlling operation of delay-locked loop circuit Grant 8,184,495 - Kim , et al. May 22, 2	2012-05-22
Semiconductor Memory Device For Controlling Operation Of Delay-locked Loop Circuit App 20100097870 - Kim; Jun-Bae ; et al.	2010-04-22
Test pattern generating circuit and semiconductor memory device having the same Grant 7,673,209 - Park , et al. March 2, 2	2010-03-02
Semiconductor device, test system and method of testing on die termination circuit Grant 7,612,578 - Chang , et al. November 3, 2	2009-11-03
Input circuit of semiconductor memory device and test system having the same Grant 7,587,645 - Chang , et al. September 8, 2	2009-09-08
Test Pattern Generating Circuit And Semiconductor Memory Device Having The Same App 20080086663 - PARK; Hwan-wook ; et al.	2008-04-10
Generation of test mode signals in memory device with minimized wiring Grant 7,334,169 - Chang , et al. February 19, 2	2008-02-19
Input Circuit Of Semiconductor Memory Device And Test System Having The Same App 20070234165 - Chang; Young-Uk ; et al.	2007-10-04
Semiconductor device, test system and method of testing on die termination circuit App 20070103189 - Chang; Young-Uk ; et al.	2007-05-10
Integrated circuit devices having multiple precharge circuits and methods of operating the same Grant 7,130,232 - Kim , et al. October 31, 2	2006-10-31
Generation of test mode signals in memory device with minimized wiring App 20060059398 - Chang; Young-Uk ; et al.	2006-03-16
Circuits and methods for generating high frequency extended test pattern data from low frequency test pattern data input to an integrated circuit memory device Grant 6,822,914 - Kim , et al. November 23, 2	2004-11-23
Integrated circuit devices having multiple precharge circuits and methods of operating the same App 20040165416 - Kim, Joung-Yeal ; et al.	2004-08-26
Circuits and methods for generating high frequency extended test pattern data from low frequency test pattern data input to an integrated circuit memory device App 20040100839 - Kim, Chang-Sik ; et al.	2004-05-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.