Chang; Yih-Jau

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Yih-Jau.The latest application filed is for "semiconductor structure and fabrication method thereof".

Company Profile

0.10.3

Chang; Yih-Jau - Zhudong Township Hsinchu County TW
Chang; Yih-Jau - Hsinchu County TW
Chang; Yih-Jau - Hsinchu TW
Chang; Yih-Jau - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor structure and fabrication method thereof Grant 8,252,652 - Chang , et al. August 28, 2	2012-08-28
Semiconductor structure and fabrication method thereof Grant 8,154,078 - Chang , et al. April 10, 2	2012-04-10
Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability in integrated circuit Grant 8,063,444 - Chang November 22, 2	2011-11-22
Semiconductor Structure And Fabrication Method Thereof App 20110233672 - CHANG; Yih-Jau ; et al.	2011-09-29
Semiconductor Structure And Fabrication Method Thereof App 20110198692 - CHANG; Yih-Jau ; et al.	2011-08-18
Lateral Diffused Metal Oxide Semiconductor (ldmos) Devices With Electrostatic Discharge (esd) Protection Capability In Integrated Circuit App 20100148256 - Chang; Yih-Jau	2010-06-17
Method of manufacturing electrostatic discharge protective circuit Grant 6,225,166 - Hsu , et al. May 1, 2	2001-05-01
Method of fabricating semiconductor device for preventing antenna effect Grant 6,150,261 - Hsu , et al. November 21, 2	2000-11-21
Method of manufacturing electrostatic discharge protective circuit Grant 6,114,226 - Chang , et al. September 5, 2	2000-09-05
Method for fabricating an electrostatistic discharge protection device to protect an integrated circuit Grant 6,040,222 - Hsu , et al. March 21, 2	2000-03-21
Method of making porous-Si capacitors for high density drams cell Grant 5,723,373 - Chang , et al. March 3, 1	1998-03-03
Dual poly-gate deep submicron CMOS with buried contact technology Grant 5,670,397 - Chang , et al. September 23, 1	1997-09-23
Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors Grant 4,478,679 - Chang , et al. October 23, 1	1984-10-23

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