Chang; Mu-Tien

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Mu-Tien.The latest application filed is for "coordinated in-module ras features for synchronous ddr compatible memory".

Company Profile

39.47.54

Chang; Mu-Tien - Santa Clara CA
Chang; Mu-Tien - San Jose CA
Chang; Mu-Tien - Taipei TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Asynchronous communication protocol compatible with synchronous DDR protocol Grant 11,397,698 - Niu , et al. July 26, 2	2022-07-26
Coordinated In-module Ras Features For Synchronous Ddr Compatible Memory App 20220229551 - CHANG; Mu-Tien ; et al.	2022-07-21
Coordinated in-module RAS features for synchronous DDR compatible memory Grant 11,294,571 - Chang , et al. April 5, 2	2022-04-05
Systems and methods for write and flush support in hybrid memory Grant 11,175,853 - Chang , et al. November 16, 2	2021-11-16
3d-stacked Memory With Reconfigurable Compute Logic App 20210311634 - Chang; Mu-Tien ; et al.	2021-10-07
Dram Assist Error Correction Mechanism For Ddr Sdram Interface App 20210294697 - NIU; DIMIN ; et al.	2021-09-23
3-D stacked memory with reconfigurable compute logic Grant 11,079,936 - Chang , et al. August 3, 2	2021-08-03
Page size synchronization and page size aware scheduling method for non-volatile memory dual in-line memory module (NVDIMM) over memory channel Grant 11,029,879 - Niu , et al. June 8, 2	2021-06-08
DRAM assist error correction mechanism for DDR SDRAM interface Grant 11,010,242 - Niu , et al. May 18, 2	2021-05-18
Bandwidth Boosted Stacked Memory App 20210141735 - MALLADI; Krishna T. ; et al.	2021-05-13
DRAM assist error correction mechanism for DDR SDRAM interface Grant 10,977,118 - Niu , et al. April 13, 2	2021-04-13
Isa Extension For High-bandwidth Memory App 20210096999 - Chang; Mu-Tien ; et al.	2021-04-01
Multi-cell structure for non-volatile resistive memory Grant 10,929,026 - Niu , et al. February 23, 2	2021-02-23
Bandwidth boosted stacked memory Grant 10,915,451 - Malladi , et al. February 9, 2	2021-02-09
Method to deliver in-DRAM ECC information through DDR bus Grant 10,908,993 - Niu , et al. February 2, 2	2021-02-02
Method to deliver in-DRAM ECC information through DDR bus Grant 10,872,014 - Niu , et al. December 22, 2	2020-12-22
ISA extension for high-bandwidth memory Grant 10,866,900 - Chang , et al. December 15, 2	2020-12-15
Byte-addressable flash-based memory module with prefetch mode that is adjusted based on feedback from prefetch accuracy that is calculated by comparing first decoded address and second decoded address, where the first decoded address is sent to memory controller, and the second decoded address is se Grant 10,866,897 - Chang , et al. December 15, 2	2020-12-15
Bandwidth Boosted Stacked Memory App 20200356488 - Malladi; Krishna T. ; et al.	2020-11-12
Method of executing conditional data scrubbing inside a smart storage device Grant 10,824,348 - Olarig , et al. November 3, 2	2020-11-03
System and method for operating a DRR-compatible asynchronous memory module Grant 10,810,144 - Lim , et al. October 20, 2	2020-10-20
Method to deliver in-DRAM ECC information through DDR bus Grant 10,795,764 - Niu , et al. October 6, 2	2020-10-06
Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory Grant 10,762,000 - Chang , et al. Sep	2020-09-01
Coordinated In-module Ras Features For Synchronous Ddr Compatible Memory App 20200218447 - CHANG; Mu-Tien ; et al.	2020-07-09
Dedupe DRAM cache Grant 10,705,969 - Chang , et al.	2020-07-07
Asynchronous Communication Protocol Compatible With Synchronous Ddr Protocol App 20200167297 - NIU; Dimin ; et al.	2020-05-28
Asynchronous communication protocol compatible with synchronous DDR protocol Grant 10,621,119 - Niu , et al.	2020-04-14
Coordinated in-module RAS features for synchronous DDR compatible memory Grant 10,592,114 - Chang , et al.	2020-03-17
Memory system and method of controlling the same Grant 10,558,388 - Niu , et al. Feb	2020-02-11
Morphable ECC encoder/decoder for NVDIMM over DDR channel Grant 10,552,256 - Niu , et al. Fe	2020-02-04
Methods for addressing high capacity SDRAM-like memory without increasing pin cost Grant 10,504,572 - Chang , et al. Dec	2019-12-10
Virtual bucket multiple hash tables for efficient memory in-line deduplication application Grant 10,496,543 - Sala , et al. De	2019-12-03
Coordinated near-far memory controller for process-in-HBM Grant 10,437,482 - Chang , et al. O	2019-10-08
Method To Deliver In-dram Ecc Information Through Ddr Bus App 20190266050 - NIU; Dimin ; et al.	2019-08-29
Method To Deliver In-dram Ecc Information Through Ddr Bus App 20190266049 - NIU; Dimin ; et al.	2019-08-29
Method to deliver in-DRAM ECC information through DDR bus Grant 10,394,648 - Niu , et al. A	2019-08-27
Refresh aware replacement policy for volatile memory cache Grant 10,394,719 - Chang , et al. A	2019-08-27
Page Size Synchronization And Page Size Aware Scheduling Method For Non-volatile Memory Dual In-line Memory Module (nvdimm) Over App 20190235788 - NIU; Dimin ; et al.	2019-08-01
Dedupe Dram Cache App 20190227941 - CHANG; Mu Tien ; et al.	2019-07-25
Self-optimized power management for DDR-compatible memory systems Grant 10,347,306 - Chang , et al. July 9, 2	2019-07-09
Dram Assist Error Correction Mechanism For Ddr Sdram Interface App 20190179704 - Niu; Dimin ; et al.	2019-06-13
Dram Assist Error Correction Mechanism For Ddr Sdram Interface App 20190179705 - Niu; Dimin ; et al.	2019-06-13
Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application Grant 10,318,434 - Sala , et al.	2019-06-11
Mitigating DRAM cache metadata access overhead with SRAM metadata cache and bloom filter Grant 10,282,294 - Chang , et al.	2019-05-07
DRAM assist error correction mechanism for DDR SDRAM interface Grant 10,268,541 - Niu , et al.	2019-04-23
Isa Extension For High-bandwidth Memory App 20190114265 - Chang; Mu-Tien ; et al.	2019-04-18
Hybrid DRAM array including dissimilar memory cells Grant 10,223,252 - Chang , et al.	2019-03-05
Dual Row-column Major Dram App 20190043553 - CHANG; Mu-Tien ; et al.	2019-02-07
Coordinated Near-far Memory Controller For Process-in-hbm App 20190034097 - Chang; Mu-Tien ; et al.	2019-01-31
HBM with in-memory cache manager Grant 10,180,906 - Stocksdale , et al. Ja	2019-01-15
Systems And Methods For Write And Flush Support In Hybrid Memory App 20180329651 - Chang; Mu-Tien ; et al.	2018-11-15
Morphable Ecc Encoder/decoder For Nvdimm Over Ddr Channel App 20180322007 - NIU; Dimin ; et al.	2018-11-08
Hybrid memory controller with command buffer for arbitrating access to volatile and non-volatile memories in a hybrid memory group Grant 10,114,560 - Niu , et al. October 30, 2	2018-10-30
Techniques To Reduce Read-modify-write Overhead In Hybrid Dram/nand Memory App 20180293175 - Chang; Mu-Tien ; et al.	2018-10-11
Hybrid Dram Array Including Dissimilar Memory Cells App 20180285253 - Chang; Mu-Tien ; et al.	2018-10-04
Mitigating Dram Cache Metadata Access Overhead With Sram Metadata Cache And Bloom Filter App 20180232310 - Chang; Mu-Tien ; et al.	2018-08-16
Wear leveling for storage or memory device Grant 10,049,717 - Niu , et al. August 14, 2	2018-08-14
Refresh Aware Replacement Policy For Volatile Memory Cache App 20180210843 - Chang; Mu-Tien ; et al.	2018-07-26
System architecture with memory channel DRAM FPGA module Grant 10,013,212 - Zheng , et al. July 3, 2	2018-07-03
Optimized Hopscotch Multiple Hash Tables For Efficient Memory In-line Deduplication Application App 20180181495 - Sala; Frederic ; et al.	2018-06-28
Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application Grant 9,983,821 - Sala , et al. May 29, 2	2018-05-29
Hybrid memory module and transaction-based memory interface Grant 9,971,511 - Niu , et al. May 15, 2	2018-05-15
Method To Deliver In-dram Ecc Information Through Ddr Bus App 20180129561 - NIU; Dimin ; et al.	2018-05-10
Methods For Addressing High Capacity Sdram-like Memory Without Increasing Pin Cost App 20180102152 - Chang; Mu-Tien ; et al.	2018-04-12
Byte-addressable Flash-based Memory Module App 20180089087 - Chang; Mu-Tien ; et al.	2018-03-29
High performance transaction-based memory systems Grant 9,904,635 - Chang , et al. February 27, 2	2018-02-27
Hybrid Memory Controller For Arbitrating Access To Volatile And Non-volatile Memories In A Hybrid Memory Group App 20180046388 - Niu; Dimin ; et al.	2018-02-15
Dram Assist Error Correction Mechanism For Ddr Sdram Interface App 20180046541 - Niu; Dimin ; et al.	2018-02-15
Method Of Executing Data Scrubbing Inside A Smart Storage Device App 20180039437 - OLARIG; Sompong Paul ; et al.	2018-02-08
Hbm With In-memory Cache Manager App 20180032437 - Stocksdale; Tyler ; et al.	2018-02-01
Self-optimized Power Management For Ddr-compatible Memory Systems App 20170365305 - CHANG; Mu-Tien ; et al.	2017-12-21
Tail response time reduction method for SSD Grant 9,846,650 - Chang , et al. December 19, 2	2017-12-19
System And Method For Operating A Drr-compatible Asynchronous Memory Module App 20170357604 - Lim; Sun Young ; et al.	2017-12-14
Methods for addressing high capacity SDRAM-like memory without increasing pin cost Grant 9,837,135 - Chang , et al. December 5, 2	2017-12-05
Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group Grant 9,830,086 - Niu , et al. November 28, 2	2017-11-28
Virtual Bucket Multiple Hash Tables For Efficient Memory In-line Deduplication Application App 20170286005 - Sala; Frederic ; et al.	2017-10-05
Optimized Hopscotch Multiple Hash Tables For Efficient Memory In-line Deduplication Application App 20170286003 - Sala; Frederic ; et al.	2017-10-05
Smart in-module refresh for DRAM Grant 9,761,296 - Chang , et al. September 12, 2	2017-09-12
Coordinated In-module Ras Features For Synchronous Ddr Compatible Memory App 20170255383 - CHANG; Mu-Tien ; et al.	2017-09-07
Asynchronous Communication Protocol Compatible With Synchronous Ddr Protocol App 20170255575 - NIU; Dimin ; et al.	2017-09-07
3-d Stacked Memory With Reconfigurable Compute Logic App 20170255390 - Chang; Mu-Tien ; et al.	2017-09-07
Memory System And Method Of Controlling The Same App 20170255418 - Niu; Dimin ; et al.	2017-09-07
Adaptive Mechanism For Synchronized Or Asynchronized Memory Devices App 20170255398 - Niu; Dimin ; et al.	2017-09-07
Wear Leveling For Storage Or Memory Device App 20170256305 - Niu; Dimin ; et al.	2017-09-07
Methods For Addressing High Capacity Sdram-like Memory Without Increasing Pin Cost App 20170256311 - Chang; Mu-Tien ; et al.	2017-09-07
Multi-cell Structure For Non-volatile Resistive Memory App 20170242595 - NIU; Dimin ; et al.	2017-08-24
Hybrid Memory Module And Transaction-based Memory Interface App 20170192686 - NIU; Dimin ; et al.	2017-07-06
Reliability-aware memory partitioning mechanisms for future memory technologies Grant 9,696,923 - Niu , et al. July 4, 2	2017-07-04
System Architecture With Memory Channel Dram Fpga Module App 20170153854 - ZHENG; Hongzhong ; et al.	2017-06-01
High Performance Transaction-based Memory Systems App 20170060788 - CHANG; Mu-Tien ; et al.	2017-03-02
Transaction-based Hybrid Memory Module App 20170060434 - CHANG; Mu-Tien ; et al.	2017-03-02
Smart In-module Refresh For Dram App 20170040050 - CHANG; Mu-Tien ; et al.	2017-02-09
Smart In-module Refresh For Dram App 20160307619 - CHANG; Mu-Tien ; et al.	2016-10-20
Reliability-aware Memory Partitioning Mechanisms For Future Memory Technologies App 20160266824 - NIU; Dimin ; et al.	2016-09-15
Tail Response Time Reduction Method For Ssd App 20160267011 - CHANG; Mu-Tien ; et al.	2016-09-15
Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus Grant 8,072,818 - Chang , et al. December 6, 2	2011-12-06
Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus App 20100172194 - Chang; Mu-Tien ; et al.	2010-07-08

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