Chang; Ming-Tung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Ming-Tung.The latest application filed is for "testing system and testing method".

Company Profile

1.9.9

Chang; Ming-Tung - Jiangsu Province CN
Chang; Ming-Tung - Hsinchu County N/A TW
Chang; Ming Tung - Taichung TW
Chang; Ming-Tung - Changhua TW
Chang; Ming-Tung - Hsinchu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Testing system and testing method Grant 10,776,558 - Chen , et al. Sept	2020-09-15
Testing System And Testing Method App 20200151299 - Chen; Shih-Hsin ; et al.	2020-05-14
Through silicon via testing structure Grant 8,487,645 - Chang , et al. July 16, 2	2013-07-16
Method for creating test clock domain during integrated circuit design, and associated computer readable medium Grant 8,468,407 - Chang , et al. June 18, 2	2013-06-18
Method For Creating Test Clock Domain During Integrated Circuit Design, And Associated Computer Readable Medium App 20120233513 - Chang; Ming-Tung ; et al.	2012-09-13
Through-silicon via testing structure App 20120012841 - Chang; Ming-Tung ; et al.	2012-01-19
Powder agitating device for fire extinguisher App 20090188681 - Chang; Ming Tung	2009-07-30
Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit Grant 7,512,851 - Wang , et al. March 31, 2	2009-03-31
Method and apparatus for unifying self-test with scan-test during prototype debug and production test App 20090037786 - Wang; Laung-Terng ; et al.	2009-02-05
Method and apparatus for unifying self-test with scan-test during prototype debug and production test Grant 7,444,567 - Wang , et al. October 28, 2	2008-10-28
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques Grant 7,284,175 - Wang , et al. October 16, 2	2007-10-16
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques App 20070168803 - Wang; Laung-Terng ; et al.	2007-07-19
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques Grant 7,191,373 - Wang , et al. March 13, 2	2007-03-13
Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit App 20050055617 - Wang, Laung-Terng ; et al.	2005-03-10
Method and apparatus for unifying self-test with scan-test during prototype debug and production test App 20040268181 - Wang, Laung-Terng ; et al.	2004-12-30
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques App 20020138801 - Wang, Laung-Terng ; et al.	2002-09-26

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.