Chang; Jung-Ho

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Jung-Ho.The latest application filed is for "integrated circuit and method of manufacturing the same".

Company Profile

3.11.2

Chang; Jung-Ho - Yunlin County TW
Chang; Jung-Ho - Taichung TW
Chang; Jung-Ho - Taichung City TW
Chang; Jung-Ho - Uen-Lin TW
Chang; Jung-Ho - Hsinchu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Non-volatile memory device and method for manufacturing the same Grant 11,251,273 - Chen , et al. February 15, 2	2022-02-15
Integrated circuit and method of manufacturing the same Grant 10,971,508 - Tsai , et al. April 6, 2	2021-04-06
Integrated Circuit And Method Of Manufacturing The Same App 20200343256 - Tsai; Yao-Ting ; et al.	2020-10-29
Non-volatile Memory Device And Method For Manufacturing The Same App 20200035794 - CHEN; Jian-Ting ; et al.	2020-01-30
Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure Grant 6,194,265 - Chang , et al. February 27, 2	2001-02-27
Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer Grant 6,165,830 - Lin , et al. December 26, 2	2000-12-26
In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application Grant 6,127,221 - Lin , et al. October 3, 2	2000-10-03
Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications Grant 6,046,083 - Lin , et al. April 4, 2	2000-04-04
One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications Grant 6,037,219 - Lin , et al. March 14, 2	2000-03-14
Process to reduce defect formation occurring during shallow trench isolation formation Grant 6,037,238 - Chang , et al. March 14, 2	2000-03-14
Method for fabricating a stacked, or crown shaped, capacitor structure Grant 5,930,625 - Lin , et al. July 27, 1	1999-07-27
Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure Grant 5,913,119 - Lin , et al. June 15, 1	1999-06-15
Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion Grant 5,897,352 - Lin , et al. April 27, 1	1999-04-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.