loadpatents
name:-0.0055851936340332
name:-0.016695976257324
name:-0.0007481575012207
Chang; Jia-Hwang Patent Filings

Chang; Jia-Hwang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Jia-Hwang.The latest application filed is for "memory driving circuit".

Company Profile
0.13.4
  • Chang; Jia-Hwang - Hsinchu County TW
  • Chang; Jia-Hwang - Saratoga CA
  • Chang; Jia-Hwang - Cupertino CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Memory driving circuit
Grant 9,865,347 - Jien , et al. January 9, 2
2018-01-09
Memory Driving Circuit
App 20170076796 - JIEN; Fan-Yi ;   et al.
2017-03-16
Non-volatile memory cell and non-volatile memory device
Grant 9,543,006 - Wu , et al. January 10, 2
2017-01-10
Non-volatile memory device with memristor
Grant 9,514,817 - Chang , et al. December 6, 2
2016-12-06
Non-volatile Memory Cell And Non-volatile Memory Device
App 20160351257 - WU; Jui-Jen ;   et al.
2016-12-01
Memory driving circuit
Grant 9,401,203 - Chang , et al. July 26, 2
2016-07-26
Memory device and driving method thereof
Grant 9,368,203 - Huang , et al. June 14, 2
2016-06-14
Programmable and redundant circuitry based on magnetic tunnel junction (MTJ)
Grant 7,894,248 - Yu , et al. February 22, 2
2011-02-22
Programmable and Redundant Circuitry Based On Magnetic Tunnel Junction (MTJ)
App 20100067293 - Yu; David Chang-Cheng ;   et al.
2010-03-18
Method And System For Providing Spin Transfer Tunneling Magnetic Memories Utilizing Unidirectional Polarity Selection Devices
App 20090185410 - Huai; Yiming ;   et al.
2009-07-23
Testability architecture and techniques for programmable interconnect architecture
Grant 5,432,441 - El-Ayat , et al. July 11, 1
1995-07-11
Testability architecture and techniques for programmable interconnect architecture
Grant 5,365,165 - El-Ayat , et al. November 15, 1
1994-11-15
Testability architecture and techniques for programmable interconnect architecture
Grant 5,341,092 - El-Ayat , et al. * August 23, 1
1994-08-23
Testability architecture and techniques for programmable interconnect architecture
Grant 5,309,091 - El-Ayat , et al. May 3, 1
1994-05-03
Testability architecture and techniques for programmable interconnect architecture
Grant 5,223,792 - El-Ayat , et al. June 29, 1
1993-06-29
Testability architecture and techniques for programmable interconnect architecture
Grant 5,208,530 - El-Ayat , et al. May 4, 1
1993-05-04
Testability architecture and techniques for programmable interconnect architecture
Grant 5,083,083 - El-Ayat , et al. January 21, 1
1992-01-21

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed