loadpatents
name:-0.011789083480835
name:-0.0085368156433105
name:-0.00055909156799316
Chang; Hsusheng Patent Filings

Chang; Hsusheng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Hsusheng.The latest application filed is for "method for forming high aspect ratio patterning structure".

Company Profile
0.8.13
  • Chang; Hsusheng - Shanghai CN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method for forming high aspect ratio patterning structure
Grant 9,991,116 - Liu , et al. June 5, 2
2018-06-05
Method For Forming High Aspect Ratio Patterning Structure
App 20180144929 - Liu; Peng ;   et al.
2018-05-24
Apparatus for detecting the flatness of wafer and the method thereof
Grant 9,134,122 - Li , et al. September 15, 2
2015-09-15
Process Of Manufacturing The Gate Oxide Layer
App 20150064930 - LI; ZHONGPING ;   et al.
2015-03-05
Method Of Forming Nickel Salicide On A Silicon-germanium Layer
App 20150004767 - Cai; Junsheng ;   et al.
2015-01-01
Method for etching polysilicon gate
Grant 8,900,887 - Tang , et al. December 2, 2
2014-12-02
Layout pattern modification method
Grant 8,898,598 - Zhang , et al. November 25, 2
2014-11-25
Optical proximity correction method based on hybrid simulation model
Grant 8,863,045 - Chen , et al. October 14, 2
2014-10-14
Dummy wafer structure and method of forming the same
Grant 8,822,348 - Ren , et al. September 2, 2
2014-09-02
Apparatus For Detecting The Flatness Of Wafer And The Method Thereof
App 20140153000 - Li; WenLiang ;   et al.
2014-06-05
Method For Etching Polysilicon Gate
App 20140106475 - TANG; Zaifeng ;   et al.
2014-04-17
Method Of Adding An Additional Mask In The Ion-implantation Process
App 20140099783 - LAI; ChaoRong ;   et al.
2014-04-10
Dummy Wafer Structure And Method Of Forming The Same
App 20140077343 - REN; Chuan ;   et al.
2014-03-20
Method for reducing morphological difference between N-doped and undoped polysilicon gates after etching
Grant 8,658,502 - Tang , et al. February 25, 2
2014-02-25
Algorithm of Cu interconnect dummy inserting
Grant 8,645,879 - Fang , et al. February 4, 2
2014-02-04
Method For Reducing Morphological Difference Between N-doped And Undoped Polysilicon Gates After Etching
App 20130316539 - TANG; Zaifeng ;   et al.
2013-11-28
Algorithm Of Cu Interconnect Dummy Inserting
App 20130227502 - FANG; JINGXUN ;   et al.
2013-08-29
Method Of Forming Nitrogen-free Dielectric Anti-reflection Layer
App 20130224399 - CHEN; ChienWei ;   et al.
2013-08-29
Process for Eliminating Fog Particles on a Surface of High P Concentration PSG Film
App 20130064992 - GU; Meimei ;   et al.
2013-03-14

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed