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name:-0.050143003463745
name:-0.31378197669983
name:-0.02611780166626
Chang; Gwan-Sin Patent Filings

Chang; Gwan-Sin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chang; Gwan-Sin.The latest application filed is for "system and method for performing extreme ultraviolet photolithography processes".

Company Profile
12.49.45
  • Chang; Gwan-Sin - Hsinchu TW
  • CHANG; Gwan-Sin - Hsinchu City TW
  • Chang; Gwan Sin - Hsin-Chu TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
System and method for performing extreme ultraviolet photolithography processes
Grant 11,392,040 - Chen , et al. July 19, 2
2022-07-19
Nanowire stack GAA device and methods for producing the same
Grant 11,201,243 - Yang , et al. December 14, 2
2021-12-14
System And Method For Performing Extreme Ultraviolet Photolithography Processes
App 20210349396 - CHEN; Tai-Yu ;   et al.
2021-11-11
Protection of MRAM from external magnetic field using magnetic-field-shielding structure
Grant 11,139,341 - Liu , et al. October 5, 2
2021-10-05
Semiconductor Device And Manufacturing Method Thereof
App 20210305409 - WU; Zhi-Qiang ;   et al.
2021-09-30
Semiconductor structure and fabrication method thereof
Grant 11,075,282 - Liu , et al. July 27, 2
2021-07-27
Method for manufacturing semiconductor device
Grant 11,043,579 - Wang , et al. June 22, 2
2021-06-22
Semiconductor device and manufacturing method thereof
Grant 11,024,721 - Wu , et al. June 1, 2
2021-06-01
Nanowire Stack Gaa Device And Methods For Producing The Same
App 20210066490 - Yang; Chansyun David ;   et al.
2021-03-04
FinFET device including an dielectric region and method for fabricating same
Grant 10,937,909 - Wang , et al. March 2, 2
2021-03-02
Apparatus and method for prevention of contamination on collector of extreme ultraviolet light source
Grant 10,871,647 - Liu , et al. December 22, 2
2020-12-22
Method For Manufacturing Semiconductor Device
App 20200350422 - WANG; Chih-Hao ;   et al.
2020-11-05
Finfet Device And Method For Fabricating Same
App 20200321459 - WANG; Chih-Hao ;   et al.
2020-10-08
Semiconductor device and manufacturing method thereof
Grant 10,720,514 - Wang , et al.
2020-07-21
Method for fabricating FinFET including forming an oxide layer
Grant 10,629,737 - Wang , et al.
2020-04-21
Semiconductor Structure And Fabrication Method Thereof
App 20200111893 - LIU; Kuo-An ;   et al.
2020-04-09
Semiconductor Device And Manufacturing Method Thereof
App 20200098890 - WU; Zhi-Qiang ;   et al.
2020-03-26
Apparatus And Method For Prevention Of Contamination On Collector Of Extreme Ultraviolet Light Source
App 20200041783 - LIU; Kuo-An ;   et al.
2020-02-06
Protection Of Mram From External Magnetic Field Using Magnetic-field-shielding Structure
App 20190386061 - Liu; Kuo-An ;   et al.
2019-12-19
Semiconductor Structure And Fabrication Method Thereof
App 20190386114 - LIU; Kuo-An ;   et al.
2019-12-19
Semiconductor structure and fabrication method thereof
Grant 10,510,866 - Liu , et al. Dec
2019-12-17
Semiconductor Device And Manufacturing Method Thereof
App 20190013396 - WANG; Chih-Hao ;   et al.
2019-01-10
Semiconductor device and manufacturing method thereof
Grant 10,056,473 - Wang , et al. August 21, 2
2018-08-21
Method for forming semiconductor structure with epitaxial growth structure
Grant 9,997,615 - Yeh , et al. June 12, 2
2018-06-12
Tuning strain in semiconductor devices
Grant 9,941,404 - Colinge , et al. April 10, 2
2018-04-10
Method for inducing strain in vertical semiconductor columns
Grant 9,935,198 - Colinge , et al. April 3, 2
2018-04-03
Thermally tuning strain in semiconductor devices
Grant 9,871,141 - Diaz , et al. January 16, 2
2018-01-16
Methods for double-patterning-compliant standard cell design
Grant 9,747,402 - Chen , et al. August 29, 2
2017-08-29
Finfet Device And Method For Fabricating Same
App 20170229561 - WANG; Chih-Hao ;   et al.
2017-08-10
Method For Forming Semiconductor Structure With Epitaxial Growth Structure
App 20170154978 - YEH; Che-Yu ;   et al.
2017-06-01
FinFET device and method for fabricating same
Grant 9,634,127 - Ching , et al. April 25, 2
2017-04-25
Tuning Strain in Semiconductor Devices
App 20160336445 - Colinge; Jean-Pierre ;   et al.
2016-11-17
Method for Inducing Strain in Vertical Semiconductor Columns
App 20160268427 - Colinge; Jean-Pierre ;   et al.
2016-09-15
Tuning strain in semiconductor devices
Grant 9,419,098 - Colinge , et al. August 16, 2
2016-08-16
Finfet Device And Method For Fabricating Same
App 20160233321 - Ching; Kuo-Cheng ;   et al.
2016-08-11
Thermally Tuning Strain in Semiconductor Devices
App 20160218216 - Diaz; Carlos H. ;   et al.
2016-07-28
Method for inducing strain in vertical semiconductor columns
Grant 9,368,619 - Colinge , et al. June 14, 2
2016-06-14
Thermally tuning strain in semiconductor devices
Grant 9,349,850 - Colinge , et al. May 24, 2
2016-05-24
FinFET device and method of fabricating same
Grant 9,318,606 - Wang , et al. April 19, 2
2016-04-19
Buried SiGe oxide FinFET scheme for device enhancement
Grant 9,202,917 - Ching , et al. December 1, 2
2015-12-01
Semiconductor device and fabricating the same
Grant 9,153,670 - Wang , et al. October 6, 2
2015-10-06
Tuning Strain in Semiconductor Devices
App 20150214333 - Colinge; Jean-Pierre ;   et al.
2015-07-30
Inducing Localized Strain In Vertical Nanowire Transistors
App 20150129831 - Colinge; Jean-Pierre ;   et al.
2015-05-14
Semiconductor Device and Fabricating the Same
App 20150132901 - Wang; Chih-Hao ;   et al.
2015-05-14
Tuning strain in semiconductor devices
Grant 9,006,842 - Colinge , et al. April 14, 2
2015-04-14
Methods for Double-Patterning-Compliant Standard Cell Design
App 20150095870 - Chen; Huang-Yu ;   et al.
2015-04-02
Buried Sige Oxide Finfet Scheme For Device Enhancement
App 20150028426 - Ching; Kuo-Cheng ;   et al.
2015-01-29
Method of merging color sets of layout
Grant 8,943,445 - Chen , et al. January 27, 2
2015-01-27
Thermally Tuning Strain in Semiconductor Devices
App 20150021697 - Colinge; Jean-Pierre ;   et al.
2015-01-22
Methods for double-patterning-compliant standard cell design
Grant 8,907,441 - Chen , et al. December 9, 2
2014-12-09
Tuning Strain in Semiconductor Devices
App 20140353731 - Colinge; Jean-Pierre ;   et al.
2014-12-04
Semiconductor device and fabricating the same
Grant 8,901,607 - Wang , et al. December 2, 2
2014-12-02
Method of generating technology file for integrated circuit design tools
Grant 8,826,207 - Hou , et al. September 2, 2
2014-09-02
Method for Inducing Strain in Vertical Semiconductor Columns
App 20140225184 - Colinge; Jean-Pierre ;   et al.
2014-08-14
FinFET Device and Method of Fabricating Same
App 20140197457 - Wang; Chih-Hao ;   et al.
2014-07-17
Semiconductor Device and Fabricating the Same
App 20140197456 - Wang; Chih-Hao ;   et al.
2014-07-17
Method Of Merging Color Sets Of Layout
App 20140101623 - CHEN; Pi-Tsung ;   et al.
2014-04-10
Source/drain stack stressor for semiconductor device
Grant 8,633,516 - Wu , et al. January 21, 2
2014-01-21
Decomposing integrated circuit layout
Grant 8,631,379 - Chen , et al. January 14, 2
2014-01-14
Accurate parasitic capacitance extraction for ultra large scale integrated circuits
Grant 8,572,537 - Su , et al. October 29, 2
2013-10-29
IC design flow enhancement with CMP simulation
Grant 8,336,002 - Chang , et al. December 18, 2
2012-12-18
Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
App 20120260225 - Su; Ke-Ying ;   et al.
2012-10-11
3-dimensional device design layout
Grant 8,286,114 - Chuang , et al. October 9, 2
2012-10-09
Routing system and method for double patterning technology
Grant 8,239,806 - Chen , et al. August 7, 2
2012-08-07
Performance-aware logic operations for generating masks
Grant 8,227,869 - Lu , et al. July 24, 2
2012-07-24
Accurate parasitic capacitance extraction for ultra large scale integrated circuits
Grant 8,214,784 - Su , et al. July 3, 2
2012-07-03
System and method for design-for-manufacturability data encryption
Grant 8,136,168 - Cheng , et al. March 13, 2
2012-03-13
Performance-Aware Logic Operations for Generating Masks
App 20120043618 - Lu; Lee-Chung ;   et al.
2012-02-23
Performance-aware logic operations for generating masks
Grant 8,122,394 - Lu , et al. February 21, 2
2012-02-21
Decomposing Integrated Circuit Layout
App 20110197168 - Chen; Pi-Tsung ;   et al.
2011-08-11
Methods for Double-Patterning-Compliant Standard Cell Design
App 20110193234 - Chen; Huang-Yu ;   et al.
2011-08-11
Place-and-route layout method with same footprint cells
Grant 7,966,596 - Lu , et al. June 21, 2
2011-06-21
Routing System And Method For Double Patterning Technology
App 20110119648 - Chen; Huang-Yu ;   et al.
2011-05-19
System, method, and computer program product for matching cell layout of an integrated circuit design
Grant 7,904,844 - Chang , et al. March 8, 2
2011-03-08
Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
App 20110023003 - Su; Ke-Ying ;   et al.
2011-01-27
Accurate parasitic capacitance extraction for ultra large scale integrated circuits
Grant 7,818,698 - Su , et al. October 19, 2
2010-10-19
Method for smart dummy insertion to reduce run time and dummy count
Grant 7,801,717 - Chang , et al. September 21, 2
2010-09-21
Method for optimally converting a circuit design into a semiconductor device
Grant 7,797,668 - Chang , et al. September 14, 2
2010-09-14
System, method, and computer program product for matching cell layout of an integrated circuit design
Grant 7,788,612 - Chang , et al. August 31, 2
2010-08-31
Performance-Aware Logic Operations for Generating Masks
App 20100065913 - Lu; Lee-Chung ;   et al.
2010-03-18
Place-and-route Layout Method With Same Footprint Cells
App 20100058267 - Lu; Lee-Chung ;   et al.
2010-03-04
Method of Generating Technology File for Integrated Circuit Design Tools
App 20090077507 - Hou; Cliff ;   et al.
2009-03-19
Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
App 20090007035 - Su; Ke-Ying ;   et al.
2009-01-01
3-Dimensional Device Design Layout
App 20080263492 - Chuang; Harry ;   et al.
2008-10-23
Integrated Circuit Design Usage And Sanity Verification
App 20080244483 - Chang; Gwan Sin ;   et al.
2008-10-02
Integrated Circuit Design Usage And Sanity Verification
App 20080244482 - Chang; Gwan Sin ;   et al.
2008-10-02
Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count
App 20080176343 - Chang; Gwan Sin ;   et al.
2008-07-24
IC Design Flow Enhancement With CMP Simulation
App 20070266356 - Chang; Gwan Sin ;   et al.
2007-11-15
System and Method for Design-for-Manufacturability Data Encryption
App 20070266248 - Cheng; Yi-Kan ;   et al.
2007-11-15
Method for optimally converting a circuit design into a semiconductor device
App 20070006117 - Chang; Gwan Sin ;   et al.
2007-01-04

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