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name:-0.011967897415161
name:-0.0037338733673096
Chandrasekharan; Karthik Patent Filings

Chandrasekharan; Karthik

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chandrasekharan; Karthik.The latest application filed is for "clocked miller latch design for improved soft error rate".

Company Profile
2.9.7
  • Chandrasekharan; Karthik - Chandler AZ
  • Chandrasekharan; Karthik - Scottsdale AZ US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Clocked miller latch design for improved soft error rate
Grant 10,491,218 - Chandrasekharan , et al. Nov
2019-11-26
Clocked Miller Latch Design For Improved Soft Error Rate
App 20190319622 - Chandrasekharan; Karthik ;   et al.
2019-10-17
Charge steering latch for low soft error rate
Grant 9,667,251 - Chandrasekharan , et al. May 30, 2
2017-05-30
Scalable serializer
Grant 9,143,164 - Chen , et al. September 22, 2
2015-09-22
Hysteresis-based latch design for improved soft error rate with low area/performance overhead
Grant 8,723,548 - Chandrasekharan , et al. May 13, 2
2014-05-13
Scalable Serializer
App 20130328704 - Chen; Hua-Feng ;   et al.
2013-12-12
Hysteresis-Based Latch Design for Improved Soft Error Rate with Low Area/Performance Overhead
App 20130234753 - Chandrasekharan; Karthik ;   et al.
2013-09-12
Single stage and scalable serializer
Grant 8,514,108 - Chen , et al. August 20, 2
2013-08-20
Single Stage and Scalable Serializer
App 20120299756 - Chen; Hua-Feng ;   et al.
2012-11-29
Data retention flip flop for low power applications
Grant 8,085,076 - Djaja , et al. December 27, 2
2011-12-27
Low leakage data retention flip flop
Grant 8,076,965 - Djaja , et al. December 13, 2
2011-12-13
Data retention flip flop for low power applications
App 20100001774 - Djaja; Gregory ;   et al.
2010-01-07
Low leakage data retention flip flop
App 20090256608 - Djaja; Gregory ;   et al.
2009-10-15

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