Chander; Avinash

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chander; Avinash.The latest application filed is for "flying and twisted bit line architecture for dual-port static random-access memory (dp sram)".

Company Profile

6.6.6

Chander; Avinash - Jhubei TW
Chander; Avinash - Jhubei City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) Grant 10,991,423 - Singh , et al. April 27, 2	2021-04-27
Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) Grant 10,790,015 - Singh , et al. September 29, 2	2020-09-29
Flying And Twisted Bit Line Architecture For Dual-port Static Random-access Memory (dp Sram) App 20200020391 - Singh; Sahil Preet ; et al.	2020-01-16
Flying And Twisted Bit Line Architecture For Dual-port Static Random-access Memory (dp Sram) App 20200020392 - Singh; Sahil Preet ; et al.	2020-01-16
Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) Grant 10,490,267 - Singh , et al. Nov	2019-11-26
Flying And Twisted Bit Line Architecture For Dual-port Static Random-access Memory (dp Sram) App 20190108875 - Singh; Sahil Preet ; et al.	2019-04-11
Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) Grant 10,157,666 - Singh , et al. Dec	2018-12-18
Flying And Twisted Bit Line Architecture For Dual-port Static Random-access Memory (dp Sram) App 20180137910 - Singh; Sahil Preet ; et al.	2018-05-17
Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) Grant 9,928,899 - Singh , et al. March 27, 2	2018-03-27
Memory circuit with negative voltage assist Grant 9,812,191 - Chander , et al. November 7, 2	2017-11-07
Memory Device With Reduced-resistance Interconnect App 20170186750 - Singh; Sahil Preet ; et al.	2017-06-29
Flying And Twisted Bit Line Architecture For Dual-port Static Random-access Memory (dp Sram) App 20170186483 - Singh; Sahil Preet ; et al.	2017-06-29

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