Chanclou; Roland
Patent Applications and Registrations
Patent applications and USPTO patent grants for Chanclou; Roland.The latest application filed is for "stacked conductive resistive polysilicon lands in multilevel semiconductor chips".
- Chanclou; Roland - Perthes FR
- Chanclou; Roland - Perthes en Gatinais FR
- Chanclou; Roland - 77930 Perthes en Gatinais FR
| Patent | Date |
|---|---|
| Stacked conductive resistive polysilicon lands in multilevel semiconductor chips Grant 5,381,046 - Cederbaum , et al. January 10, 1 | 1995-01-10 |
| Method of forming thin film pseudo-planar FET devices and structures resulting therefrom Grant 5,320,975 - Cederbaum , et al. June 14, 1 | 1994-06-14 |
| Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom Grant 5,275,963 - Cederbaum , et al. January 4, 1 | 1994-01-04 |
| Follow-up system for etch process monitoring Grant 5,223,914 - Auda , et al. June 29, 1 | 1993-06-29 |
| Method of producing high resolution and reproducible patterns Grant 5,139,904 - Auda , et al. August 18, 1 | 1992-08-18 |
| Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefrom Grant 5,100,817 - Cederbaum , et al. March 31, 1 | 1992-03-31 |
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