CHAN; Yi-Ling

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHAN; Yi-Ling.The latest application filed is for "necked finfet device".

Company Profile

0.6.6

CHAN; Yi-Ling - Miaoli TW
Chan, Yi-Ling - Mianoli TW
Chan; Yi-Ling - Meo-Li TW
Chan; Yi-Ling - Junan Jen Misoli TW
Chan; Yi-Ling - Miao-Li TW
Chan, Yi-Ling - Junan Jen TW
Chan, Yi-Ling - Junan Jen Miaoli TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Necked Finfet device App 20070063261 - CHEN; Haur-Ywh ; et al.	2007-03-22
Method of fabricating a necked FINFET device Grant 7,122,412 - Chen , et al. October 17, 2	2006-10-17
Method of fabricating a necked finfet device App 20050253193 - Chen, Haur-Ywh ; et al.	2005-11-17
Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement App 20040266128 - Chen, Haur-Ywh ; et al.	2004-12-30
Electrostatic discharge device protection structure Grant 6,800,516 - Chan , et al. October 5, 2	2004-10-05
Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement Grant 6,784,071 - Chen , et al. August 31, 2	2004-08-31
BONDED SOI WAFER WITH <100> DEVICE LAYER AND <110> SUBSTRATE FOR PERFORMANCE IMPROVEMENT App 20040151917 - Chen, Haur-Ywh ; et al.	2004-08-05
High performance PD SOI tunneling-biased MOSFET Grant 6,674,130 - Yang , et al. January 6, 2	2004-01-06
Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions Grant 6,673,683 - Sheu , et al. January 6, 2	2004-01-06
SOI MOSFET with compact body-tied-source structure App 20030222308 - Su, Ke-Wei ; et al.	2003-12-04
High performance PD SOI tunneling-biased mosfet App 20030122214 - Yang, Kuo-Nan ; et al.	2003-07-03
High performance PD SOI tunneling-biased MOSFET Grant 6,518,105 - Yang , et al. February 11, 2	2003-02-11

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