Chan; Victor W. C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chan; Victor W. C..The latest application filed is for "gate contact over active enabled by alternative spacer scheme and claw-shaped cap".

Company Profile

8.18.17

Chan; Victor W. C. - Guilderland NY
Chan; Victor W. C. - Newburgh NY
Chan; Victor W. C. - Poughkeepsie NY
Chan; Victor W. C. - New Paltz NY
Chan; Victor W.C. - Poughkeepsle NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Single metallization scheme for gate, source, and drain contact integration Grant 11,309,221 - Greene , et al. April 19, 2	2022-04-19
Self-aligned gate cap including an etch-stop layer Grant 11,257,716 - Belyansky , et al. February 22, 2	2022-02-22
Self-aligned gate cap including an etch-stop layer Grant 11,222,820 - Belyansky , et al. January 11, 2	2022-01-11
Single metallization scheme for gate, source, and drain contact integration Grant 10,985,076 - Greene , et al. April 20, 2	2021-04-20
Gate contact over active enabled by alternative spacer scheme and claw-shaped cap Grant 10,943,990 - Greene , et al. March 9, 2	2021-03-09
Gate Contact Over Active Enabled by Alternative Spacer Scheme and Claw-Shaped Cap App 20200135886 - Greene; Andrew ; et al.	2020-04-30
Self-aligned Gate Cap Including An Etch-stop Layer App 20200090998 - Belyansky; Michael P. ; et al.	2020-03-19
Single Metallization Scheme For Gate, Source, And Drain Contact Integration App 20200083117 - Greene; Andrew ; et al.	2020-03-12
Single Metallization Scheme For Gate, Source, And Drain Contact Integration App 20200066602 - GREENE; Andrew ; et al.	2020-02-27
Self-aligned Gate Cap Including An Etch-stop Layer App 20200006137 - Belyansky; Michael P. ; et al.	2020-01-02
Avoiding gate metal via shorting to source or drain contacts Grant 10,043,744 - Chan , et al. August 7, 2	2018-08-07
Avoiding Gate Metal Via Shorting To Source Or Drain Contacts App 20180061754 - Chan; Victor W.C. ; et al.	2018-03-01
Avoiding Gate Metal Via Shorting To Source Or Drain Contacts App 20170352621 - Chan; Victor W. C. ; et al.	2017-12-07
Avoiding gate metal via shorting to source or drain contacts Grant 9,837,351 - Chan , et al. December 5, 2	2017-12-05
High threshold voltage NMOS transistors for low power IC technology Grant 8,969,969 - Chan , et al. March 3, 2	2015-03-03
High threshold voltage NMOS transistors for low power IC technology Grant 8,927,361 - Booth, Jr. , et al. January 6, 2	2015-01-06
Structure fabrication method Grant 8,753,929 - Anderson , et al. June 17, 2	2014-06-17
Structure Fabrication Method App 20130230960 - Anderson; Brent A. ; et al.	2013-09-05
High Threshold Voltage Nmos Transistors For Low Power Ic Technology App 20130196476 - Booth, JR.; Roger Allen ; et al.	2013-08-01
Semiconductor transistors with expanded top portions of gates Grant 8,466,503 - Anderson , et al. June 18, 2	2013-06-18
High Threshold Voltage NMOS Transistors For Low Power IC Technology App 20100237425 - Chan; Victor W.C. ; et al.	2010-09-23
Substrate engineering for optimum CMOS device performance Grant 7,482,216 - Chan , et al. January 27, 2	2009-01-27
Semiconductor transistors with expanded top portions of gates Grant 7,473,593 - Anderson , et al. January 6, 2	2009-01-06
Semiconductor Transistors With Expanded Top Portions Of Gates App 20080296707 - Anderson; Brent Alan ; et al.	2008-12-04
Method of applying stresses to PFET and NFET transistor channels for improved performance Grant 7,442,611 - Chan , et al. October 28, 2	2008-10-28
SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET App 20080246056 - Chan; Victor W. C. ; et al.	2008-10-09
Semiconductor Transistors With Expanded Top Portions Of Gates App 20070158763 - Anderson; Brent Alan ; et al.	2007-07-12
Method of applying stresses to PFET and NFET transistor channels for improved performance App 20070122982 - Chan; Victor W. C. ; et al.	2007-05-31
Structure and method of applying stresses to PFET and NFET transistor channels for improved performance Grant 7,193,254 - Chan , et al. March 20, 2	2007-03-20
Substrate engineering for optimum CMOS device performance Grant 7,148,559 - Chan , et al. December 12, 2	2006-12-12
Substrate engineering for optimum CMOS device performance App 20060240611 - Chan; Victor W.C. ; et al.	2006-10-26
Structure And Method Of Applying Stresses To Pfet And Nfet Transistor Channels For Improved Performance App 20060113568 - Chan; Victor W.C. ; et al.	2006-06-01
Substrate Engineering For Optimum Cmos Device Performance App 20050001290 - Chan, Victor W.C. ; et al.	2005-01-06

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