loadpatents
name:-0.015151023864746
name:-0.02067494392395
name:-0.0023088455200195
Chan; Michael Y. Patent Filings

Chan; Michael Y.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chan; Michael Y..The latest application filed is for "conductive micro led architecture for on-wafer testing".

Company Profile
0.13.9
  • Chan; Michael Y. - Sunnyvale CA
  • Chan; Michael Y. - Mountain View CA US
  • Chan; Michael Y. - Portland OR
  • Chan; Michael Y. - Houston TX
  • Chan, Michael Y. - Oakland CA
  • Chan; Michael Y. - Alpharetta GA
  • Chan; Michael Y. - Wallingford PA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Conductive micro LED architecture for on-wafer testing
Grant 11,404,601 - John , et al. August 2, 2
2022-08-02
Conductive Micro LED Architecture for On-Wafer Testing
App 20210091259 - John; Ranjith Samuel E. ;   et al.
2021-03-25
Memory cell that includes a carbon-based memory element and methods of forming the same
Grant 8,481,394 - Chan , et al. July 9, 2
2013-07-09
Three-dimensional stacked substrate arrangements
Grant 8,421,225 - Ramanathan , et al. April 16, 2
2013-04-16
Three-dimensional Stacked Substrate Arrangements
App 20120280387 - Ramanathan; Shriram ;   et al.
2012-11-08
Three-dimensional stacked substrate arrangements
Grant 8,203,208 - Ramanathan , et al. June 19, 2
2012-06-19
Three-dimensional Stacked Substrate Arrangements
App 20110260319 - Ramanathan; Shriram ;   et al.
2011-10-27
Memory Cell That Includes A Carbon-based Memory Element And Methods Of Forming The Same
App 20110215320 - Chan; Michael Y. ;   et al.
2011-09-08
Three-dimensional stacked substrate arrangements
Grant 7,973,407 - Ramanathan , et al. July 5, 2
2011-07-05
Three-dimensional stacked substrate arrangements
App 20090174070 - Ramanathan; Shriram ;   et al.
2009-07-09
Bonded wafer processing method
Grant 7,129,172 - Morrow , et al. October 31, 2
2006-10-31
Point-to-point electrical loading for a multi-drop bus
Grant 7,099,966 - Chan , et al. August 29, 2
2006-08-29
Bonded wafer processing method
App 20050215056 - Morrow, Patrick ;   et al.
2005-09-29
Three-dimensional stacked substrate arrangements
App 20050003650 - Ramanathan, Shriram ;   et al.
2005-01-06
Point-to-point electrical loading for a multi-drop bus
App 20040003162 - Chan, Michael Y. ;   et al.
2004-01-01
Towel fold configuration
Grant 6,623,833 - Chan September 23, 2
2003-09-23
Towel fold configuration
App 20020051863 - Chan, Michael Y.
2002-05-02
Apparatus for controlling the impedance of high speed signals on a printed circuit board
Grant 5,986,893 - Leigh , et al. November 16, 1
1999-11-16
Apparatus for controlling the impedance of high speed signals on a printed circuit board
Grant 5,764,489 - Leigh , et al. June 9, 1
1998-06-09
Interleaved towel fold configuration
Grant 5,118,554 - Chan , et al. June 2, 1
1992-06-02

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