Chan; Hiang C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chan; Hiang C..The latest application filed is for "method of fabricating a gate having a barrier of titanium silicide".

Company Profile

0.19.0

Chan; Hiang C. - Fremont CA
Chan; Hiang C. - Boise ID

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of fabricating a gate having a barrier of titanium silicide Grant 6,107,176 - Fazan , et al. August 22, 2	2000-08-22
Method of fabricating a gate having a barrier of titanium silicide Grant 5,798,296 - Fazan , et al. August 25, 1	1998-08-25
Oxidation enhancement in narrow masked field regions of a semiconductor wafer Grant 5,358,894 - Fazan , et al. October 25, 1	1994-10-25
Semiconductor device for minimizing diffusion of conductivity enhancing impurities from one region of a polysilicon layer to another Grant 5,313,087 - Chan , et al. May 17, 1	1994-05-17
DRAM stacked capacitor fabrication process Grant 5,262,343 - Rhodes , et al. November 16, 1	1993-11-16
Lateral extension stacked capacitor Grant 5,236,860 - Fazan , et al. August 17, 1	1993-08-17
Stacked comb spacer capacitor Grant 5,234,855 - Rhodes , et al. * August 10, 1	1993-08-10
Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor Grant 5,170,233 - Liu , et al. December 8, 1	1992-12-08
Stacked H-cell capacitor and process to fabricate same Grant 5,137,842 - Chan , et al. August 11, 1	1992-08-11
Stacked multi-poly spacers with double cell plate capacitor Grant 5,126,280 - Chan , et al. * June 30, 1	1992-06-30
Double DRAM cell Grant 5,122,476 - Fazan , et al. June 16, 1	1992-06-16
Mushroom double stacked capacitor Grant 5,108,943 - Sandhu , et al. * April 28, 1	1992-04-28
Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer Grant 5,087,586 - Chan , et al. February 11, 1	1992-02-11
Process to fabricate a double ring stacked cell structure Grant 5,084,405 - Fazan , et al. January 28, 1	1992-01-28
Method for forming low resistance DRAM digit-line Grant 5,084,406 - Rhodes , et al. January 28, 1	1992-01-28
Method of making stacked textured container capacitor Grant 5,082,797 - Chan , et al. January 21, 1	1992-01-21
Enclosed ferroelectric stacked capacitor Grant 5,081,559 - Fazan , et al. January 14, 1	1992-01-14
Double DRAM cell Grant 5,057,888 - Fazan , et al. October 15, 1	1991-10-15
Method of making stacked E-cell capacitor DRAM cell Grant 5,053,351 - Fazan , et al. October 1, 1	1991-10-01

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