loadpatents
name:-0.0089809894561768
name:-0.0085160732269287
name:-0.0038130283355713
Chan; Chung-Lun Patent Filings

Chan; Chung-Lun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chan; Chung-Lun.The latest application filed is for "memory sequencing with coherent and non-coherent sub-systems".

Company Profile
2.8.11
  • Chan; Chung-Lun - Hillsboro OR
  • Chan; Chung-Lun - Beaverton OR US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Resolving memory accesses crossing cache line boundaries
Grant 10,318,427 - Matas , et al.
2019-06-11
Memory sequencing with coherent and non-coherent sub-systems
Grant 10,261,904 - Zhang , et al.
2019-04-16
Apparatuses, methods, and systems to share translation lookaside buffer entries
Grant 10,108,554 - Chan , et al. October 23, 2
2018-10-23
Memory Sequencing With Coherent And Non-coherent Sub-systems
App 20180173628 - ZHANG; CHUNHUI ;   et al.
2018-06-21
Apparatuses, Methods, And Systems To Share Translation Lookaside Buffer Entries
App 20180157598 - CHAN; CHUNG-LUN ;   et al.
2018-06-07
Method and apparatus for performing an efficient scatter
Grant 9,891,914 - Matas , et al. February 13, 2
2018-02-13
Scalable event handling in multi-threaded processor cores
Grant 9,886,396 - Gramunt , et al. February 6, 2
2018-02-06
Memory sequencing with coherent and non-coherent sub-systems
Grant 9,875,185 - Zhang , et al. January 23, 2
2018-01-23
Memory fault suppression via re-execution and hardware FSM
Grant 9,715,432 - Matas , et al. July 25, 2
2017-07-25
Method And Apparatus For Performing An Efficient Scatter
App 20160299762 - MATAS; RAMON ;   et al.
2016-10-13
Resolving Memory Accesses Crossing Cache Line Boundaries
App 20160179677 - MATAS; RAMON ;   et al.
2016-06-23
Memory Fault Suppression Via Re-execution And Hardware Fsm
App 20160179632 - MATAS; Ramon ;   et al.
2016-06-23
Scalable Event Handling In Multi-threaded Processor Cores
App 20160179533 - Gramunt; Roger ;   et al.
2016-06-23
Memory Sequencing With Coherent And Non-coherent Sub-systems
App 20160011977 - ZHANG; CHUNHUI ;   et al.
2016-01-14

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed