loadpatents
name:-0.0030560493469238
name:-0.039865016937256
name:-0.00193190574646
CHAN; Chi Bun Patent Filings

CHAN; Chi Bun

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHAN; Chi Bun.The latest application filed is for "clock synchronization using wifi beacons".

Company Profile
2.47.1
  • CHAN; Chi Bun - Mountain View CA
  • Chan; Chi Bun - San Jose CA
  • - San Jose CA US
  • Chan; Chi Bun - Longmont CO
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Clock Synchronization Using Wifi Beacons
App 20160150008 - SHEMAR; Mikhal ;   et al.
2016-05-26
Verification and debugging using heterogeneous simulation models
Grant 8,868,396 - Shirazi , et al. October 21, 2
2014-10-21
Simulation that transfers port values of a design block via a configuration block of a programmable device
Grant 8,812,289 - Chan , et al. August 19, 2
2014-08-19
Using constraints wtihin a high-level modeling system for circuit design
Grant 8,739,088 - Ou , et al. May 27, 2
2014-05-27
Linking untimed data-path and timed control-path models
Grant 8,650,019 - Sundararajan , et al. February 11, 2
2014-02-11
Automatically documenting circuit designs
Grant 8,650,517 - Sundararajan , et al. February 11, 2
2014-02-11
Method of performing a simulation of a design under test and a circuit for enabling testing of a circuit design
Grant 8,620,638 - Chan , et al. December 31, 2
2013-12-31
Method of performing a simulation of a design under test and a circuit for enabling testing of a circuit design
Grant 08620638 -
2013-12-31
Method and apparatus for providing program-based hardware co-simulation of a circuit design
Grant 8,600,722 - Chan , et al. December 3, 2
2013-12-03
Method and circuit for secure definition and integration of cores
Grant 8,417,965 - Sundararajan , et al. April 9, 2
2013-04-09
Common debugger method and system
Grant 8,402,442 - Chan , et al. March 19, 2
2013-03-19
Enabling a high-level modeling system
Grant 8,356,266 - Ou , et al. January 15, 2
2013-01-15
Reloadable just-in-time compilation simulation engine for high level modeling systems
Grant 8,352,229 - Ma , et al. January 8, 2
2013-01-08
High level system design using functional and object-oriented composition
Grant 8,332,786 - Chan , et al. December 11, 2
2012-12-11
Simulation and emulation of a circuit design
Grant 8,265,918 - Neema , et al. September 11, 2
2012-09-11
Configurable memory map interface and method of implementing a configurable memory map interface
Grant 8,248,869 - Chan , et al. August 21, 2
2012-08-21
Method and apparatus for modeling processor-based circuit models
Grant 8,229,725 - Ou , et al. July 24, 2
2012-07-24
Managing programmable device configuration
Grant 8,224,638 - Shirazi , et al. July 17, 2
2012-07-17
Hardware co-simulation involving a processor disposed on a programmable integrated circuit
Grant 8,195,441 - Ou , et al. June 5, 2
2012-06-05
Detecting differences between high level block diagram models
Grant 8,156,459 - Ou , et al. April 10, 2
2012-04-10
Method and apparatus for profiling a hardware/software embedded system
Grant 8,145,467 - Ou , et al. March 27, 2
2012-03-27
Clustering of electronic circuit design modules for hardware-based and software-based co-simulation platforms
Grant 8,145,466 - Chan , et al. March 27, 2
2012-03-27
Rapid rerouting based runtime reconfigurable signal probing
Grant 8,103,992 - Chan , et al. January 24, 2
2012-01-24
Method of and system for implementing a circuit in a device having programmable logic
Grant 8,102,188 - Chan , et al. January 24, 2
2012-01-24
Power estimation in high-level modeling systems
Grant 8,082,530 - Ou , et al. December 20, 2
2011-12-20
On-demand switching between hardware and software implementations of a peripheral device
Grant 8,065,445 - Ou , et al. November 22, 2
2011-11-22
Trace module for integrated circuit devices
Grant 8,042,007 - Chan , et al. October 18, 2
2011-10-18
Dual-bus system for communicating with a processor
Grant 8,041,855 - Ou , et al. October 18, 2
2011-10-18
Clock frequency exploration for circuit designs having multiple clock domains
Grant 8,020,127 - Chan , et al. September 13, 2
2011-09-13
Conversion of a high-level graphical circuit design block to a high-level language program
Grant 7,992,111 - Ma , et al. August 2, 2
2011-08-02
Variable clocking in hardware co-simulation
Grant 7,937,259 - Chan , et al. May 3, 2
2011-05-03
Accelerating hardware co-simulation using dynamic replay on first-in-first-out-driven command processor
Grant 7,930,162 - Chan , et al. April 19, 2
2011-04-19
Method and apparatus for supplying a clock to a device under test
Grant 7,852,109 - Chan , et al. December 14, 2
2010-12-14
Method of and system for implementing a circuit in a device having programmable logic
Grant 7,746,099 - Chan , et al. June 29, 2
2010-06-29
Systems and methods of co-simulation utilizing multiple PLDs in a boundary scan chain
Grant 7,747,423 - Shirazi , et al. June 29, 2
2010-06-29
Command buffering for hardware co-simulation
Grant 7,707,019 - Ballagh , et al. April 27, 2
2010-04-27
Recovering a prior state of a circuit design within a programmable integrated circuit
Grant 7,673,201 - Chan , et al. March 2, 2
2010-03-02
Point-to-point ethernet hardware co-simulation interface
Grant 7,636,653 - Chan , et al. December 22, 2
2009-12-22
Parameterizable compact network processor for low-level communication with an integrated circuit
Grant 7,590,137 - Chan , et al. September 15, 2
2009-09-15

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