Chakraborty; Tapan J

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chakraborty; Tapan J.The latest application filed is for "method and apparatus for characterizing thermal marginality in an integrated circuit".

Company Profile

0.8.5

Chakraborty; Tapan J - San Diego CA
Chakraborty; Tapan J. - San Diego CA
Chakraborty; Tapan J. - Princeton Junction NJ
Chakraborty; Tapan J. - Mercerville NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for characterizing thermal marginality in an integrated circuit Grant 9,285,418 - Chakraborty , et al. March 15, 2	2016-03-15
Method And Apparatus For Characterizing Thermal Marginality In An Integrated Circuit App 20130285687 - Chakraborty; Tapan J. ; et al.	2013-10-31
Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing Grant 7,962,885 - Chakraborty , et al. June 14, 2	2011-06-14
Method and apparatus for describing and testing a system-on-chip Grant 7,958,479 - Chakraborty , et al. June 7, 2	2011-06-07
Method and apparatus for describing parallel access to a system-on-chip Grant 7,949,915 - Chakraborty , et al. May 24, 2	2011-05-24
Method And Apparatus For Describing And Testing A System-on-chip App 20090144594 - Chakraborty; Tapan J. ; et al.	2009-06-04
Method and apparatus for describing parallel access to a system-on-chip App 20090144593 - Chakraborty; Tapan J. ; et al.	2009-06-04
Method and Apparatus for Describing Components Adapted for Dynamically Modifying a Scan Path for System-on-Chip Testing App 20090144592 - Chakraborty; Tapan J. ; et al.	2009-06-04
Fault injection method and system Grant 7,284,159 - Chakraborty , et al. October 16, 2	2007-10-16
Fault injection method and system App 20050050393 - Chakraborty, Tapan J. ; et al.	2005-03-03
Delay testing of high-performance digital components by a slow-speed tester Grant 5,606,567 - Agrawal , et al. February 25, 1	1997-02-25
Method and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs) Grant 5,499,249 - Agrawal , et al. March 12, 1	1996-03-12
Method for testing delay faults in non-scan sequential circuits Grant 5,365,528 - Agrawal , et al. November 15, 1	1994-11-15

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