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Patent applications and USPTO patent grants for Chakraborty; Rajat Subhra.The latest application filed is for "architecture and design automation of high performance large adders and counters on fpga through constrained placement".
Patent | Date |
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Architecture And Design Automation Of High Performance Large Adders And Counters On Fpga Through Constrained Placement App 20170140073 - Chakraborty; Rajat Subhra ;   et al. | 2017-05-18 |
Multi-level inline data deduplication Grant 9,311,323 - Chakraborty , et al. April 12, 2 | 2016-04-12 |
Multi-level Inline Data Deduplication App 20140114934 - Chakraborty; Rajat Subhra ;   et al. | 2014-04-24 |
Protection of intellectual property cores through a design flow Grant 8,402,401 - Chakraborty , et al. March 19, 2 | 2013-03-19 |
Protection Of Intellectual Property (ip) Cores Through A Design Flow App 20110113392 - CHAKRABORTY; RAJAT SUBHRA ;   et al. | 2011-05-12 |
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