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name:-0.0077970027923584
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Chakraborty; Kanad Patent Filings

Chakraborty; Kanad

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chakraborty; Kanad.The latest application filed is for "programmable circuits for correcting scan-test circuitry defects in integrated circuit designs".

Company Profile
0.7.8
  • Chakraborty; Kanad - Portland OR
  • Chakraborty; Kanad - Bridgewater NJ
  • Chakraborty; Kanad - Mt. Arlington NJ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Embedded memory testing using back-to-back write/read operations
Grant 9,728,273 - Chakraborty , et al. August 8, 2
2017-08-08
Programmable circuits for correcting scan-test circuitry defects in integrated circuit designs
Grant 9,618,579 - Chakraborty April 11, 2
2017-04-11
Adaptive technique for adjusting signal development across bit lines for read operation robustness in memory circuits
Grant 9,530,486 - Chakraborty December 27, 2
2016-12-27
Programmable Circuits for Correcting Scan-Test Circuitry Defects in Integrated Circuit Designs
App 20160320448 - Chakraborty; Kanad
2016-11-03
Embedded Memory Testing Using Back-To-Back Write/Read Operations
App 20150340103 - Chakraborty; Kanad ;   et al.
2015-11-26
Configurable Test Address And Data Generation For Multimode Memory Built-In Self-Testing
App 20150310933 - Purushotham; Naveen ;   et al.
2015-10-29
Highly secure and extensive scan testing of integrated circuits
Grant 8,977,917 - Han , et al. March 10, 2
2015-03-10
Highly Secure And Extensive Scan Testing Of Integrated Circuits
App 20140136914 - Han; Wei ;   et al.
2014-05-15
Fine-grained power management of synchronous and asynchronous datapath circuits
Grant 7,511,535 - Chakraborty , et al. March 31, 2
2009-03-31
Fine-Grained Power Management of Synchronous and Asynchronous Datapath Circuits
App 20080204124 - Chakraborty; Kanad ;   et al.
2008-08-28
System and method for suppressing crosstalk glitch in digital circuits
Grant 7,409,659 - Chakraborty , et al. August 5, 2
2008-08-05
Integrated circuit architecture for reducing interconnect parasitics
App 20070194453 - Chakraborty; Kanad ;   et al.
2007-08-23
System and method for suppressing crosstalk glitch in digital circuits
App 20060107245 - Chakraborty; Kanad ;   et al.
2006-05-18
Method and apparatus for applying fine-grained transforms during placement synthesis interaction
Grant 7,047,163 - Chakraborty , et al. May 16, 2
2006-05-16
Method of configuring integrated circuits using greedy algorithm for partitioning of n points in p isothetic rectangles
App 20020174410 - Chakraborty, Kanad ;   et al.
2002-11-21

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