Chae; Moosung M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chae; Moosung M..The latest application filed is for "electrical fuse formation during a multiple patterning process".

Company Profile

3.9.12

Chae; Moosung M. - Englewood Cliffs NJ
Chae; Moosung M. - Albany NY
Chae; Moosung M. - Saratoga Springs NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electrical fuse formation during a multiple patterning process Grant 11,348,870 - Shu , et al. May 31, 2	2022-05-31
Electrical Fuse Formation During A Multiple Patterning Process App 20200335435 - Shu; Jiehui ; et al.	2020-10-22
Electrical fuse formation during a multiple patterning process Grant 10,784,195 - Shu , et al. Sept	2020-09-22
IC structure with interface liner and methods of forming same Grant 10,553,478 - Zhang , et al. Fe	2020-02-04
Electrical Fuse Formation During A Multiple Patterning Process App 20190326209 - Shu; Jiehui ; et al.	2019-10-24
Ic Structure With Interface Liner And Methods Of Forming Same App 20180337126 - Zhang; Xunyuan ; et al.	2018-11-22
IC structure with interface liner and methods of forming same Grant 10,079,208 - Zhang , et al. September 18, 2	2018-09-18
Airgaps to isolate metallization features Grant 10,043,753 - Cao , et al. August 7, 2	2018-08-07
Airgaps To Isolate Metallization Features App 20180166383 - CAO; Huy ; et al.	2018-06-14
Methods of self-forming barrier formation in metal interconnection applications Grant 9,905,460 - Chae , et al. February 27, 2	2018-02-27
Ic Structure With Interface Liner And Methods Of Forming Same App 20180033728 - Zhang; Xunyuan ; et al.	2018-02-01
Methods Of Self-forming Barrier Formation In Metal Interconnection Applications App 20170133325 - CHAE; Moosung M. ; et al.	2017-05-11
Semiconductor device having non-magnetic single core inductor and method of producing the same Grant 9,484,297 - Lee , et al. November 1, 2	2016-11-01
Semiconductor Device Having Non-magnetic Single Core Inductor And Method Of Producing The Same App 20160268195 - LEE; Ki Young ; et al.	2016-09-15
Integrated Circuits With A Copper And Manganese Component And Methods For Producing Such Integrated Circuits App 20150255331 - Zhang; Xunyuan ; et al.	2015-09-10
Methods for integration of pore stuffing material Grant 9,054,052 - Licausi , et al. June 9, 2	2015-06-09
Self Forming Barrier Layer And Method Of Forming App 20150137372 - CHAE; Moosung M.	2015-05-21
Methods of self-forming barrier integration with pore stuffed ULK material Grant 8,932,934 - Chae , et al. January 13, 2	2015-01-13
Methods Of Semiconductor Contaminant Removal Using Supercritical Fluid App 20140353805 - RYAN; Errol Todd ; et al.	2014-12-04
Methods Of Self-forming Barrier Integration With Pore Stuffed Ulk Material App 20140353835 - CHAE; Moosung M. ; et al.	2014-12-04
Methods For Integration Of Pore Stuffing Material App 20140353802 - LICAUSI; Nicholas Vincent ; et al.	2014-12-04

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.