Chachad; Abhijeet A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chachad; Abhijeet A..The latest application filed is for "multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels".

Company Profile

6.12.13

Chachad; Abhijeet A. - Plano TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multicore Bus Architecture With Wire Reduction And Physical Congestion Minimization Via Shared Transaction Channels App 20220261373 - Thompson; David M. ; et al.	2022-08-18
Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels Grant 11,321,268 - Thompson , et al. May 3, 2	2022-05-03
Implied Fence On Stream Open App 20210216316 - BHORIA; Naveen ; et al.	2021-07-15
Implied fence on stream open Grant 10,963,255 - Bhoria , et al. March 30, 2	2021-03-30
Multicore Bus Architecture With Non-blocking High Performance Transaction Credit System App 20210011872 - Thompson; David M. ; et al.	2021-01-14
Multicore bus architecture with non-blocking high performance transaction credit system Grant 10,795,844 - Thompson , et al. October 6, 2	2020-10-06
Multicore Bus Architecture With Non-blocking High Performance Transaction Credit System App 20190354500 - Thompson; David M. ; et al.	2019-11-21
Implied Fence On Stream Open App 20190220276 - BHORIA; Naveen ; et al.	2019-07-18
Multicore bus architecture with non-blocking high performance transaction credit system Grant 10,311,007 - Thompson , et al.	2019-06-04
Highly integrated scalable, flexible DSP megamodule architecture Grant 10,162,641 - Anderson , et al. Dec	2018-12-25
Multicore Bus Architecture With Non-blocking High Performance Transaction Credit System App 20180293199 - THOMPSON; David M. ; et al.	2018-10-11
Multicore bus architecture with non-blocking high performance transaction credit system Grant 9,904,645 - Thompson , et al. February 27, 2	2018-02-27
Highly Integrated Scalable, Flexible Dsp Megamodule Architecture App 20170153890 - Anderson; Timothy D. ; et al.	2017-06-01
Highly integrated scalable, flexible DSP megamodule architecture Grant 9,606,803 - Anderson , et al. March 28, 2	2017-03-28
Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors Grant 9,557,936 - Anderson , et al. January 31, 2	2017-01-31
Protection Of Memories, Datapath And Pipeline Registers, And Other Storage Elements By Distributed Delayed Detection And Correction Of Soft Errors App 20160188408 - Anderson; Timothy ; et al.	2016-06-30
Multicore Bus Architecture With Wire Reduction and Physical Congestion Minimization Via Shared Transaction Channels App 20160124890 - Thompson; David M. ; et al.	2016-05-05
Multicore Bus Architecture With Non-Blocking High Performance Transaction Credit System App 20160124883 - Thompson; David M. ; et al.	2016-05-05
Distributed user controlled multilevel block and global cache coherence with accurate completion status Grant 8,904,110 - Damodaran , et al. December 2, 2	2014-12-02
Process variability tolerant programmable memory controller for a pipelined memory system Grant 8,582,384 - Chachad , et al. November 12, 2	2013-11-12
Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System App 20130283002 - Chachad; Abhijeet A. ; et al.	2013-10-24
Distributed User Controlled Multilevel Block and Global Cache Coherence with Accurate Completion Status App 20120191913 - Damodaran; Raguram ; et al.	2012-07-26
Memory error detection reporting Grant 7,240,277 - Anderson , et al. July 3, 2	2007-07-03
Memory error detection reporting App 20050132263 - Anderson, Timothy D. ; et al.	2005-06-16

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