| Patent | Date |
|---|
Method For Imparting Flame Retardancy To A Substrate Material
App 20220220385 - CHA; Randall Cher Liang ; et al. | 2022-07-14 |
Process for preparing flame retardant compositions
Grant 11,326,104 - Cha , et al. May 10, 2 | 2022-05-10 |
Process For Preparing Flame Retardant Compositions
App 20200369963 - CHA; Randall Cher Liang ; et al. | 2020-11-26 |
Flame retardant compositions and processes for preparation thereof
Grant 10,752,840 - Cha , et al. A | 2020-08-25 |
Flame Retardant Compositions and Processes for Preparation Thereof
App 20180142156 - Cha; Randall Cher Liang ; et al. | 2018-05-24 |
Integrated circuit with self-aligned line and via
Grant 8,766,454 - Lim , et al. July 1, 2 | 2014-07-01 |
Integrated Circuit With Self-aligned Line And Via
App 20070075371 - Lim; Yeow Kheng ; et al. | 2007-04-05 |
Integrated circuit with self-aligned line and via and manufacturing method therefor
Grant 7,119,010 - Lim , et al. October 10, 2 | 2006-10-10 |
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing
App 20050101083 - Ang, Chew Hoe ; et al. | 2005-05-12 |
Technique to achieve thick silicide film for ultra-shallow junctions
Grant 6,878,623 - Tan , et al. April 12, 2 | 2005-04-12 |
Dual silicon-on-insulator device wafer die
Grant 6,849,928 - Cha , et al. February 1, 2 | 2005-02-01 |
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing
Grant 6,841,441 - Ang , et al. January 11, 2 | 2005-01-11 |
Method to fabricate elevated source/drain transistor with large area for silicidation
Grant 6,780,691 - Cha , et al. August 24, 2 | 2004-08-24 |
Method to fabricate elevated source/drain structures in MOS transistors
Grant 6,727,151 - Chong , et al. April 27, 2 | 2004-04-27 |
Method to fabricate elevated source/drain transistor with large area for silicidation
App 20040033668 - Cha, Randall Cher Liang ; et al. | 2004-02-19 |
Method to fabricate a single gate with dual work-functions
Grant 6,664,153 - Ang , et al. December 16, 2 | 2003-12-16 |
Integrated circuit with self-aligned line and via and manufacturing method therefor
App 20030197279 - Lim, Yeow Kheng ; et al. | 2003-10-23 |
Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance
Grant 6,613,652 - Lim , et al. September 2, 2 | 2003-09-02 |
Method to fabricate a single gate with dual work-functions
App 20030153139 - Ang, Chew Hoe ; et al. | 2003-08-14 |
Dual silicon-on-insulator device wafer die
App 20030107083 - Cha, Randall Cher Liang ; et al. | 2003-06-12 |
Dual silicon-on-insulator device wafer die
Grant 6,558,994 - Cha , et al. May 6, 2 | 2003-05-06 |
Dual silicon-on-insulator device wafer die
App 20020127816 - Cha, Randall Cher Liang ; et al. | 2002-09-12 |
Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
App 20020127834 - Lim, Yeow Kheng ; et al. | 2002-09-12 |
Novel technique to achieve thick silicide film for ultra-shallow junctions
App 20020102802 - Tan, Cheng Cheh ; et al. | 2002-08-01 |
Simplified Method To Reduce Or Eliminate Sti Oxide Divots
App 20020098661 - Cha, Randall Cher Liang ; et al. | 2002-07-25 |
Method to reduce polysilicon depletion in MOS transistors
Grant 6,387,784 - Chong , et al. May 14, 2 | 2002-05-14 |
Low-leakage Dram Structures Using Selective Silicon Epitaxial Growth (seg) On An Insulating Layer
App 20020052077 - Tee, Kheng Chok ; et al. | 2002-05-02 |
Versatile copper-wiring layout design with low-k dielectric integration
Grant 6,355,563 - Cha , et al. March 12, 2 | 2002-03-12 |
Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique
Grant 6,319,767 - Cha , et al. November 20, 2 | 2001-11-20 |
Method to reduce compressive stress in the silicon substrate during silicidation
Grant 6,284,610 - Cha , et al. September 4, 2 | 2001-09-04 |
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