Cha; Cher Liang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cha; Cher Liang.The latest application filed is for "method to fabricate horizontal air columns underneath metal inductor".

Company Profile

0.16.5

Cha; Cher Liang - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method to fabricate horizontal air columns underneath metal inductor Grant 7,573,081 - Chan , et al. August 11, 2	2009-08-11
Method to fabricate horizontal air columns underneath metal inductor App 20070007623 - Chan; Lap ; et al.	2007-01-11
Method to form a cross network of air gaps within IMD layer Grant 7,112,866 - Chan , et al. September 26, 2	2006-09-26
Method to fabricate horizontal air columns underneath metal inductor Grant 7,105,420 - Chan , et al. September 12, 2	2006-09-12
Method to form a cross network of air gaps within IMD layer App 20040175896 - Chan, Lap ; et al.	2004-09-09
Method to form a cross network of air gaps within IMD layer Grant 6,730,571 - Chan , et al. May 4, 2	2004-05-04
Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant Grant 6,680,239 - Cha , et al. January 20, 2	2004-01-20
Forming dual gate oxide thickness on vertical transistors by ion implantation Grant 6,610,575 - Ang , et al. August 26, 2	2003-08-26
Method of fabricating CMOS device with dual gate electrode Grant 6,605,501 - Ang , et al. August 12, 2	2003-08-12
Flash device having a large planar area ono interpoly dielectric Grant 6,501,122 - Chan , et al. December 31, 2	2002-12-31
Self-aligned elevated transistor App 20020090787 - Chan, Lap ; et al.	2002-07-11
Method to form high performance copper damascene interconnects by de-coupling via and metal line filling Grant 6,380,084 - Lim , et al. April 30, 2	2002-04-30
Method to form shallow junction transistors while eliminating shorts due to junction spiking App 20020011629 - Chan, Lap ; et al.	2002-01-31
Method to form shallow junction transistors while eliminating shorts due to junction spiking App 20020003264 - Chan, Lap ; et al.	2002-01-10
Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer Grant 6,303,418 - Cha , et al. October 16, 2	2001-10-16
Method to form shallow junction transistors while eliminating shorts due to junction spiking Grant 6,297,109 - Chan , et al. October 2, 2	2001-10-02
Embedded polysilicon gate MOSFET Grant 6,252,277 - Chan , et al. June 26, 2	2001-06-26
Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology Grant 6,221,727 - Chan , et al. April 24, 2	2001-04-24
Formation of low k dielectric Grant 6,150,232 - Chan , et al. November 21, 2	2000-11-21
Method of making spiral-type RF inductors having a high quality factor (Q) Grant 6,140,197 - Chu , et al. October 31, 2	2000-10-31
Production of reversed flash memory device Grant 6,096,604 - Cha , et al. August 1, 2	2000-08-01

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