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name:-0.013087034225464
name:-0.014397859573364
name:-0.0036938190460205
CELERINT, LLC Patent Filings

CELERINT, LLC

Patent Applications and Registrations

Patent applications and USPTO patent grants for CELERINT, LLC.The latest application filed is for "device interface board compliance testing using impedance response profiling".

Company Profile
3.17.20
  • CELERINT, LLC - New York NY
  • CELERINT, LLC. - New York NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method for continuous tester operation during long soak time testing
Grant 11,448,688 - Roberts, Jr. September 20, 2
2022-09-20
Device Interface Board Compliance Testing Using Impedance Response Profiling
App 20220236325 - ROBERTS, Jr.; Howard H. ;   et al.
2022-07-28
Method For In Situ Functionality Testing Of Switches And Contacts In Semiconductor Interface Hardware
App 20210356524 - ROBERTS, Jr.; Howard H. ;   et al.
2021-11-18
Method For Continuous Tester Operation During Long Soak Time Testing
App 20210341531 - ROBERTS, Jr.; Howard H.
2021-11-04
Method For Semiconductor Device Interface Circuitry Functionality And Compliance Testing
App 20210181252 - ROBERTS, JR.; Howard H. ;   et al.
2021-06-17
Method and system for utilizing stand-alone controller in multiplexed handler test cell for indexless tandem semiconductor test
Grant 10,422,828 - Roberts, Jr. Sept
2019-09-24
Method for continuous tester operation during multiple stage temperature testing
Grant 10,386,405 - Roberts, Jr. A
2019-08-20
Modular multiplexing interface assembly for reducing semiconductor testing index time
Grant 10,197,622 - Roberts, Jr. Fe
2019-02-05
Method For Continuous Tester Operation During Multiple Stage Temperature Testing
App 20180313888 - ROBERTS, Jr.; Howard H.
2018-11-01
Method for testing semiconductor wafers using temporary sacrificial bond pads
Grant 10,043,722 - Roberts, Jr. August 7, 2
2018-08-07
Semiconductor device handler throughput optimization
Grant 9,818,631 - Roberts, Jr. , et al. November 14, 2
2017-11-14
Parallel concurrent test system and method
Grant 9,817,062 - Roberts, Jr. November 14, 2
2017-11-14
Muxing interface platform for multiplexed handlers to reduce index time system and method
Grant 9,753,081 - Roberts September 5, 2
2017-09-05
Universal multiplexing interface system and method
Grant 9,733,301 - Roberts August 15, 2
2017-08-15
Modular Multiplexing Interface Assembly For Reducing Semiconductor Testing Index Time
App 20170168111 - ROBERTS, JR.; Howard H.
2017-06-15
Parallel Concurrent Test System And Method
App 20170131346 - ROBERTS, JR.; Howard H.
2017-05-11
Parallel concurrent test system and method
Grant 9,551,740 - Roberts, Jr. January 24, 2
2017-01-24
Method For Testing Semiconductor Wafers Using Temporary Sacrificial Bond Pads
App 20160336243 - ROBERTS, JR.; Howard
2016-11-17
Semiconductor Device Handler Throughput Optimization
App 20160293461 - ROBERTS, JR.; Howard ;   et al.
2016-10-06
Parallel Concurrent Test System And Method
App 20140218063 - Roberts, JR.; Howard H.
2014-08-07
Method And System For Utilizing Stand-alone Controller In Multiplexed Handler Test Cell For Indexless Tandem Semiconductor Test
App 20140046613 - Roberts, JR.; Howard H.
2014-02-13
Tandem handler system and method for reduced index time
Grant 8,400,180 - Roberts March 19, 2
2013-03-19

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