loadpatents
name:-0.12932991981506
name:-0.10919499397278
name:-0.0467529296875
CEA; Stephen M. Patent Filings

CEA; Stephen M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for CEA; Stephen M..The latest application filed is for "fin doping and integrated circuit structures resulting therefrom".

Company Profile
45.106.133
  • CEA; Stephen M. - Hillsboro OR
  • - Hillsboro OR US
  • Cea; Stephen M - Hillsboro OR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Fin Doping And Integrated Circuit Structures Resulting Therefrom
App 20220310601 - LILAK; Aaron D. ;   et al.
2022-09-29
Buried etch-stop layer to help control transistor source/drain depth
Grant 11,430,868 - Mehandru , et al. August 30, 2
2022-08-30
Isolation Schemes For Gate-all-around Transistor Devices
App 20220246759 - MEHANDRU; Rishabh ;   et al.
2022-08-04
Vertically stacked finFETs and shared gate patterning
Grant 11,404,319 - Lilak , et al. August 2, 2
2022-08-02
Pedestal fin structure for stacked transistor integration
Grant 11,374,004 - Lilak , et al. June 28, 2
2022-06-28
Neighboring Gate-all-around Integrated Circuit Structures Having Conductive Contact Stressor Between Epitaxial Source Or Drain Regions
App 20220199771 - CHOUKSEY; Siddharth ;   et al.
2022-06-23
Isolation schemes for gate-all-around transistor devices
Grant 11,335,807 - Mehandru , et al. May 17, 2
2022-05-17
Device Isolation
App 20220140143 - Mehandru; Rishabh ;   et al.
2022-05-05
Extension Of Nanocomb Transistor Arrangements To Implement Gate All Around
App 20220093474 - Mishra; Varun ;   et al.
2022-03-24
Forksheet Transistors With Dielectric Or Conductive Spine
App 20220093647 - SUNG; Seung Hoon ;   et al.
2022-03-24
Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths
Grant 11,276,691 - Guha , et al. March 15, 2
2022-03-15
Device isolation
Grant 11,264,500 - Mehandru , et al. March 1, 2
2022-03-01
Cmos Finfet Device Having Strained Sige Fins And A Strained Si Cladding Layer On The Nmos Channel
App 20220059656 - Cea; Stephen M. ;   et al.
2022-02-24
Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer
Grant 11,195,919 - Cea , et al. December 7, 2
2021-12-07
Metallization Structures Under A Semiconductor Device Layer
App 20210343710 - Lilak; Aaron D. ;   et al.
2021-11-04
Semiconductor layer between source/drain regions and gate spacers
Grant 11,152,461 - Mehandru , et al. October 19, 2
2021-10-19
Metallization structures under a semiconductor device layer
Grant 11,107,811 - Lilak , et al. August 31, 2
2021-08-31
Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
Grant 11,094,831 - Mehandru , et al. August 17, 2
2021-08-17
Through Gate Fin Isolation
App 20210233908 - BOHR; Mark T. ;   et al.
2021-07-29
Silicon And Silicon Germanium Nanowire Structures
App 20210226006 - Kuhn; Kelin J. ;   et al.
2021-07-22
Method, device and system to provide capacitance for a dynamic random access memory cell
Grant 11,049,861 - Lilak , et al. June 29, 2
2021-06-29
Through gate fin isolation
Grant 11,037,923 - Bohr , et al. June 15, 2
2021-06-15
Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability
Grant 11,011,537 - Lilak , et al. May 18, 2
2021-05-18
Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing
Grant 10,991,696 - Lilak , et al. April 27, 2
2021-04-27
Silicon and silicon germanium nanowire structures
Grant 10,991,799 - Kuhn , et al. April 27, 2
2021-04-27
Device, Method And System To Provide A Stressed Channel Of A Transistor
App 20210083117 - Mehandru; Rishabh ;   et al.
2021-03-18
Methods and apparatus for gettering impurities in semiconductors
Grant 10,937,665 - Lilak , et al. March 2, 2
2021-03-02
Vertical Integration Scheme And Circuit Elements Architecture For Area Scaling Of Semiconductor Devices
App 20210043755 - MEHANDRU; Rishabh ;   et al.
2021-02-11
Nanowire Structures Having Wrap-around Contacts
App 20210036137 - CEA; Stephen M. ;   et al.
2021-02-04
Backside fin recess control with multi-HSI option
Grant 10,910,405 - Lilak , et al. February 2, 2
2021-02-02
Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices
Grant 10,886,272 - Cea , et al. January 5, 2
2021-01-05
High Mobility Strained Channels For Fin-based Nmos Transistors
App 20200381549 - CEA; STEPHEN M. ;   et al.
2020-12-03
High mobility strained channels for fin-based NMOS transistors
Grant 10,854,752 - Cea , et al. December 1, 2
2020-12-01
Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Grant 10,847,635 - Mehandru , et al. November 24, 2
2020-11-24
Nanowire structures having wrap-around contacts
Grant 10,840,366 - Cea , et al. November 17, 2
2020-11-17
Stacked channel structures for MOSFETs
Grant 10,790,281 - Mehandru , et al. September 29, 2
2020-09-29
Vertically Stacked Finfets & Shared Gate Patterning
App 20200235013 - Lilak; Aaron ;   et al.
2020-07-23
Silicon And Silicon Germanium Nanowire Structures
App 20200227520 - KUHN; Kelin J. ;   et al.
2020-07-16
Self-aligned Gate Endcap (sage) Architectures With Gate-all-around Devices Above Insulator Substrates
App 20200219990 - GUHA; Biswajeet ;   et al.
2020-07-09
Backside Fin Recess Control With Multi-hsi Option
App 20200176482 - LILAK; Aaron D. ;   et al.
2020-06-04
Metallization Structures Under A Semiconductor Device Layer
App 20200161298 - Lilak; Aaron D. ;   et al.
2020-05-21
Nanowire Structures Having Non-discrete Source And Drain Regions
App 20200152797 - CEA; Stephen M. ;   et al.
2020-05-14
Deep EPI enabled by backside reveal for stress enhancement and contact
Grant 10,636,907 - Lilak , et al.
2020-04-28
Silicon and silicon germanium nanowire structures
Grant 10,636,871 - Kuhn , et al.
2020-04-28
Strained Tunable Nanowire Structures And Process
App 20200105755 - Cea; Stephen M. ;   et al.
2020-04-02
Backside fin recess control with multi-hsi option
Grant 10,600,810 - Lilak , et al.
2020-03-24
Gate-all-around Integrated Circuit Structures Having Self-aligned Source Or Drain Undercut For Varied Widths
App 20200091145 - GUHA; Biswajeet ;   et al.
2020-03-19
Nanowire structures having non-discrete source and drain regions
Grant 10,580,899 - Cea , et al.
2020-03-03
Backside isolation for integrated circuit
Grant 10,573,715 - Lilak , et al. Feb
2020-02-25
Device Isolation
App 20200052117 - Mehandru; Rishabh ;   et al.
2020-02-13
Nanowire Structures Having Wrap-around Contacts
App 20200035818A1 -
2020-01-30
Semiconductor Nanowire Device Having Cavity Spacer And Method Of Fabricating Cavity Spacer For Semiconductor Nanowire Device
App 20200013905 - MEHANDRU; Rishabh ;   et al.
2020-01-09
Long channel MOS transistors for low leakage applications on a short channel CMOS chip
Grant 10,529,827 - Mehandru , et al. J
2020-01-07
Buried Etch-stop Layer To Help Control Transistor Source/drain Depth
App 20200006488 - MEHANDRU; RISHABH ;   et al.
2020-01-02
Increased Transistor Source/drain Contact Area Using Sacrificial Source/drain Layer
App 20200006525 - CRUM; DAX M. ;   et al.
2020-01-02
Pedestal Fin Structure For Stacked Transistor Integration
App 20200006340 - LILAK; AARON D. ;   et al.
2020-01-02
Isolation Schemes For Gate-all-around Transistor Devices
App 20200006559 - MEHANDRU; RISHABH ;   et al.
2020-01-02
Methods for doping a sub-fin region of a semiconductor structure by backside reveal and associated devices
Grant 10,497,781 - Lilak , et al. De
2019-12-03
Semiconductor Layer Between Source/drain Regions And Gate Spacers
App 20190355811 - Mehandru; Rishabh ;   et al.
2019-11-21
Nanowire structures having wrap-around contacts
Grant 10,483,385 - Cea , et al. Nov
2019-11-19
Direct Self Assembly (dsa) Processing Of Vertically Stacked Devices With Self-aligned Regions
App 20190341384 - Lilak; Aaron D. ;   et al.
2019-11-07
Isolation structures for an integrated circuit element and method of making same
Grant 10,468,489 - Lilak , et al. No
2019-11-05
Techniques For Forming Dual-strain Fins For Co-integrated N-mos And P-mos Devices
App 20190326290 - CEA; STEPHEN M. ;   et al.
2019-10-24
Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
Grant 10,453,967 - Mehandru , et al. Oc
2019-10-22
Hybrid trigate and nanowire CMOS device architecture
Grant 10,411,090 - Weber , et al. Sept
2019-09-10
Prevention of subchannel leakage current in a semiconductor device with a fin structure
Grant 10,403,752 - Jambunathan , et al. Sep
2019-09-03
Vertical Integration Scheme And Circuit Elements Architecture For Area Scaling Of Semiconductor Devices
App 20190252525 - MEHANDRU; Rishabh ;   et al.
2019-08-15
Vertical Interconnect Methods For Stacked Device Architectures Using Direct Self Assembly With High Operational Parallelization
App 20190221577 - LILAK; Aaron D. ;   et al.
2019-07-18
Methods And Apparatus For Gettering Impurities In Semiconductors
App 20190189464 - Lilak; Aaron D. ;   et al.
2019-06-20
Finfet Transistor With Channel Stress Induced Via Stressor Material Inserted Into Fin Plug Region Enabled By Backside Reveal
App 20190172950 - LILAK; Aaron D. ;   et al.
2019-06-06
Two-dimensional condensation for uniaxially strained semiconductor fins
Grant 10,304,929 - Kavalieros , et al.
2019-05-28
Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Grant 10,304,946 - Mehandru , et al.
2019-05-28
High Mobility Strained Channels For Fin-based Nmos Transistors
App 20190115466 - CEA; STEPHEN M. ;   et al.
2019-04-18
CMOS FinFET Device Having Strained SiGe Fins and a Strained Si Cladding Layer on the NMOS Channel
App 20190035893 - Cea; Stephen M. ;   et al.
2019-01-31
Backside Fin Recess Control With Multi-hsi Option
App 20190027503 - LILAK; Aaron D. ;   et al.
2019-01-24
High mobility strained channels for fin-based NMOS transistors
Grant 10,153,372 - Cea , et al. Dec
2018-12-11
Backside Isolation For Integrated Circuit
App 20180331183 - LILAK; AARON D. ;   et al.
2018-11-15
Stacked Channel Structures For Mosfets
App 20180323195 - Mehandru; Rishabh ;   et al.
2018-11-08
CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel
Grant 10,109,711 - Cea , et al. October 23, 2
2018-10-23
CMOS nanowire structure
Grant 10,074,573 - Kim , et al. September 11, 2
2018-09-11
Methods For Doping A Sub-fin Region Of A Semiconductor Structure By Backside Reveal And Associated Devices
App 20180248005 - LILAK; Aaron D. ;   et al.
2018-08-30
Isolation Structures For An Integrated Circuit Element And Method Of Making Same
App 20180226478 - LILAK; Aaron D. ;   et al.
2018-08-09
Long Channel Mos Transistors For Low Leakage Applications On A Short Channel Cmos Chip
App 20180226492 - MEHANDRU; Rishabh ;   et al.
2018-08-09
Method, Device And System To Provide Capacitance For A Dynamic Random Access Memory Cell
App 20180219012 - LILAK; Aaron ;   et al.
2018-08-02
Deep Epi Enabled By Backside Reveal For Stress Enhancement & Contact
App 20180212057 - LILAK; Aaron D. ;   et al.
2018-07-26
Hybrid Trigate And Nanowire Cmos Device Architecture
App 20180212023 - WEBER; Cory E. ;   et al.
2018-07-26
Semiconductor Nanowire Device Having Cavity Spacer And Method Of Fabricating Cavity Spacer For Semiconductor Nanowire Device
App 20180204955 - MEHANDRU; Rishabh ;   et al.
2018-07-19
Vertical Integration Scheme And Circuit Elements Architecture For Area Scaling Of Semiconductor Devices
App 20180204932 - MEHANDRU; Rishabh ;   et al.
2018-07-19
Semiconductor device with isolated body portion
Grant 10,026,829 - Cappellani , et al. July 17, 2
2018-07-17
CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same
Grant 9,935,107 - Cea , et al. April 3, 2
2018-04-03
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs
Grant 9,911,835 - Kotlyar , et al. March 6, 2
2018-03-06
Uniaxially strained nanowire structure
Grant 9,905,650 - Cea , et al. February 27, 2
2018-02-27
GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation
Grant 9,905,651 - Pillarisetty , et al. February 27, 2
2018-02-27
High mobility strained channels for fin-based transistors
Grant 9,893,149 - Cea , et al. February 13, 2
2018-02-13
Prevention Of Subchannel Leakage Current
App 20170330966 - JAMBUNATHAN; KARTHIK ;   et al.
2017-11-16
Two-dimensional Condensation For Uniaxially Strained Semiconductor Fins
App 20170317172 - KAVALIEROS; Jack T. ;   et al.
2017-11-02
Two-dimensional condensation for uniaxially strained semiconductor fins
Grant 9,711,598 - Kavalieros , et al. July 18, 2
2017-07-18
Non-planar device having uniaxially strained semiconductor body and method of making same
Grant 9,680,013 - Cea , et al. June 13, 2
2017-06-13
Semiconductor Device With Isolated Body Portion
App 20170162676 - CAPPELLANI; Annalisa ;   et al.
2017-06-08
Conversion of strain-inducing buffer to electrical insulator
Grant 9,673,302 - Cappellani , et al. June 6, 2
2017-06-06
Nanowire Structures Having Non-discrete Source And Drain Regions
App 20170141239 - CEA; Stephen M. ;   et al.
2017-05-18
Silicon And Silicon Germanium Nanowire Structures
App 20170133462 - KUHN; Kelin J. ;   et al.
2017-05-11
Cmos Nanowire Structure
App 20170133277 - KIM; Seiyon ;   et al.
2017-05-11
Tunneling Field Effect Transistors (tfets) For Cmos Architectures And Approaches To Fabricating N-type And P-type Tfets
App 20170133493 - Kotlyar; Roza ;   et al.
2017-05-11
Ge And Iii-v Channel Semiconductor Devices Having Maximized Compliance And Free Surface Relaxation
App 20170125524 - PILLARISETTY; RAVI ;   et al.
2017-05-04
Semiconductor device with isolated body portion
Grant 9,608,059 - Cappellani , et al. March 28, 2
2017-03-28
Silicon and silicon germanium nanowire structures
Grant 9,595,581 - Kuhn , et al. March 14, 2
2017-03-14
CMOS nanowire structure
Grant 9,583,491 - Kim , et al. February 28, 2
2017-02-28
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs
Grant 9,583,602 - Kotlyar , et al. February 28, 2
2017-02-28
Uniaxially Strained Nanowire Structure
App 20170047405 - Cea; Stephen M. ;   et al.
2017-02-16
Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation
Grant 9,570,614 - Pillarisetty , et al. February 14, 2
2017-02-14
Conversion Of Strain-inducing Buffer To Electrical Insulator
App 20170040438 - CAPPELLANI; ANNALISA ;   et al.
2017-02-09
Nanowire structures having non-discrete source and drain regions
Grant 9,564,522 - Cea , et al. February 7, 2
2017-02-07
High Mobility Strained Channels For Fin-based Nmos Transistors
App 20160351701 - CEA; STEPHEN M. ;   et al.
2016-12-01
Two-dimensional Condensation For Uniaxially Strained Semiconductor Fins
App 20160329403 - Kavalieros; Jack T. ;   et al.
2016-11-10
Uniaxially strained nanowire structure
Grant 9,490,320 - Cea , et al. November 8, 2
2016-11-08
Tunneling Field Effect Transistors (tfets) For Cmos Architectures And Approaches To Fabricating N-type And P-type Tfets
App 20160322480 - Kotlyar; Roza ;   et al.
2016-11-03
Conversion of strain-inducing buffer to electrical insulator
Grant 9,472,613 - Cappellani , et al. October 18, 2
2016-10-18
Dual Strained Cladding Layers For Semiconductor Devices
App 20160276347 - CEA; STEPHEN M ;   et al.
2016-09-22
Nmos And Pmos Strained Devices Without Relaxed Substrates
App 20160240616 - CEA; Stephen M. ;   et al.
2016-08-18
Two-dimensional condensation for uniaxially strained semiconductor fins
Grant 9,419,140 - Kavalieros , et al. August 16, 2
2016-08-16
N-type and P-type tunneling field effect transistors (TFETs)
Grant 9,412,872 - Kotlyar , et al. August 9, 2
2016-08-09
Ge and III-V Channel Semiconductor Devices having Maximized Compliance and Free Surface Relaxation
App 20160204246 - PILLARISETTY; RAVI ;   et al.
2016-07-14
Cmos Nanowire Structure
App 20160086951 - Kim; Seiyon ;   et al.
2016-03-24
Uniaxially Strained Nanowire Structure
App 20160079360 - Cea; Stephen M. ;   et al.
2016-03-17
High Mobility Strained Channels For Fin-based Transistors
App 20160071934 - Cea; Stephen M. ;   et al.
2016-03-10
Two-dimensional Condensation For Uniaxially Strained Semiconductor Fins
App 20160049513 - Kavalieros; Jack T. ;   et al.
2016-02-18
Conversion Of Strain-inducing Buffer To Electrical Insulator
App 20150380481 - CAPPELLANI; ANNALISA ;   et al.
2015-12-31
Uniaxially strained nanowire structure
Grant 9,224,808 - Cea , et al. December 29, 2
2015-12-29
CMOS nanowire structure
Grant 9,224,810 - Kim , et al. December 29, 2
2015-12-29
Nanowire Structures Having Non-discrete Source And Drain Regions
App 20150325648 - CEA; Stephen M. ;   et al.
2015-11-12
High mobility strained channels for fin-based transistors
Grant 9,184,294 - Cea , et al. November 10, 2
2015-11-10
Silicon And Silicon Germanium Nanowire Structures
App 20150303258 - KUHN; Kelin J. ;   et al.
2015-10-22
Two-dimensional condensation for uniaxially strained semiconductor fins
Grant 9,159,835 - Kavalieros , et al. October 13, 2
2015-10-13
Conversion of strain-inducing buffer to electrical insulator
Grant 9,129,827 - Cappellani , et al. September 8, 2
2015-09-08
Silicon and silicon germanium nanowire structures
Grant 9,129,829 - Kuhn , et al. September 8, 2
2015-09-08
Nanowire structures having non-discrete source and drain regions
Grant 9,087,863 - Cea , et al. July 21, 2
2015-07-21
Conversion Of Thin Transistor Elements From Silicon To Silicon Germanium
App 20150115216 - Glass; Glenn A. ;   et al.
2015-04-30
Conversion of thin transistor elements from silicon to silicon germanium
Grant 8,957,476 - Glass , et al. February 17, 2
2015-02-17
Tunneling Field Effect Transistors (tfets) For Cmos Architectures And Approaches To Fabricating N-type And P-type Tfets
App 20150041847 - Kotlyar; Roza ;   et al.
2015-02-12
High Mobility Strained Channels For Fin-based Transistors
App 20150008484 - Cea; Stephen M. ;   et al.
2015-01-08
Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs
Grant 8,890,120 - Kotlyar , et al. November 18, 2
2014-11-18
Silicon And Silicon Germanium Nanowire Structures
App 20140326952 - KUHN; Kelin J. ;   et al.
2014-11-06
High mobility strained channels for fin-based transistors
Grant 8,847,281 - Cea , et al. September 30, 2
2014-09-30
Conversion Of Strain-inducing Buffer To Electrical Insulator
App 20140285980 - Cappellani; Annalisa ;   et al.
2014-09-25
Nanowire Structures Having Wrap-around Contacts
App 20140209855 - Cea; Stephen M. ;   et al.
2014-07-31
Cmos Nanowire Structure
App 20140197377 - Kim; Seiyon ;   et al.
2014-07-17
Conversion Of Thin Transistor Elements From Silicon To Silicon Germanium
App 20140175543 - Glass; Glenn A. ;   et al.
2014-06-26
Silicon and silicon germanium nanowire structures
Grant 8,753,942 - Kuhn , et al. June 17, 2
2014-06-17
Tunneling Field Effect Transistors (tfets) For Cmos Architectures And Approaches To Fabricating N-type And P-type Tfets
App 20140138744 - Kotlyar; Roza ;   et al.
2014-05-22
Uniaxially Strained Nanowire Structure
App 20140131660 - Cea; Stephen M. ;   et al.
2014-05-15
Non-Planar Device Having Uniaxially Strained Semiconductor Body and Method of Making Same
App 20140070273 - Cea; Stephen M. ;   et al.
2014-03-13
Nanowire Structures Having Non-discrete Source And Drain Regions
App 20140042386 - Cea; Stephen M. ;   et al.
2014-02-13
High Mobility Strained Channels For Fin-based Transistors
App 20140027816 - Cea; Stephen M. ;   et al.
2014-01-30
Through Gate Fin Isolation
App 20140001572 - BOHR; Mark T. ;   et al.
2014-01-02
Semiconductor Device With Isolated Body Portion
App 20130320455 - Cappellani; Annalisa ;   et al.
2013-12-05
Non-planar device having uniaxially strained semiconductor body and method of making same
Grant 8,558,279 - Cea , et al. October 15, 2
2013-10-15
Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
Grant 8,487,348 - Cea , et al. July 16, 2
2013-07-16
Methods And Apparatus To Reduce Layout Based Strain Variations In Non-planar Transistor Structures
App 20120305990 - Cea; Stephen M ;   et al.
2012-12-06
Two-dimensional Condensation For Uniaxially Strained Semiconductor Fins
App 20120241818 - Kavalieros; Jack T. ;   et al.
2012-09-27
Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
Grant 8,269,283 - Cea , et al. September 18, 2
2012-09-18
Two-dimensional condensation for uniaxially strained semiconductor fins
Grant 8,211,772 - Kavalieros , et al. July 3, 2
2012-07-03
Silicon And Silicon Germanium Nanowire Structures
App 20120138886 - Kuhn; Kelin J. ;   et al.
2012-06-07
Non-planar device having uniaxially strained semiconductor body and method of making same
App 20120074464 - Cea; Stephen M. ;   et al.
2012-03-29
Trigate transistor having extended metal gate electrode
Grant 8,120,073 - Rakshit , et al. February 21, 2
2012-02-21
Isolated tri-gate transistor fabricated on bulk substrate
Grant 7,973,389 - Rios , et al. July 5, 2
2011-07-05
Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
App 20110147847 - Cea; Stephen M. ;   et al.
2011-06-23
Wrap-around Contacts For Finfet And Tri-gate Devices
App 20110147840 - Cea; Stephen M. ;   et al.
2011-06-23
Two-dimensional Condensation For Uniaxially Strained Semiconductor Fins
App 20110147811 - Kavalieros; Jack T. ;   et al.
2011-06-23
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
Grant 7,781,771 - Lindert , et al. August 24, 2
2010-08-24
Trigate transistor having extended metal gate electrode
App 20100163970 - Rakshit; Titash ;   et al.
2010-07-01
Multiple oxide thickness for a semiconductor device
Grant 7,719,057 - Giles , et al. May 18, 2
2010-05-18
Isolated tri-gate transistor fabricated on bulk substrate
App 20100059821 - Rios; Rafael ;   et al.
2010-03-11
Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors
App 20090152589 - Rakshit; Titash ;   et al.
2009-06-18
Multiple Oxide Thickness For A Semiconductor Device
App 20090032872 - Giles; Martin D. ;   et al.
2009-02-05
Isolated Tri-gate Transistor Fabricated On Bulk Substrate
App 20090020792 - Rios; Rafael ;   et al.
2009-01-22
Transistor with strain-inducing structure in channel
Grant 7,473,591 - Cea , et al. January 6, 2
2009-01-06
Gate-induced strain for MOS performance improvement
Grant 7,452,764 - Hoffmann , et al. November 18, 2
2008-11-18
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
App 20080142841 - Lindert; Nick ;   et al.
2008-06-19
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
Grant 7,326,634 - Lindert , et al. February 5, 2
2008-02-05
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
Grant 7,154,118 - Lindert , et al. December 26, 2
2006-12-26
High concentration indium fluorine retrograde wells
Grant 7,129,533 - Weber , et al. October 31, 2
2006-10-31
Flash lamp annealing apparatus to generate electromagnetic radiation having selective wavelengths
Grant 7,102,141 - Hwang , et al. September 5, 2
2006-09-05
Transistor with strain-inducing structure in channel
App 20060084216 - Cea; Stephen M. ;   et al.
2006-04-20
Flash lamp annealing apparatus to generate electromagnetic radiation having selective wavelengths
App 20060065849 - Hwang; Jack ;   et al.
2006-03-30
Transistor with strain-inducing structure in channel
Grant 7,019,326 - Cea , et al. March 28, 2
2006-03-28
Gate-induced strain for MOS performance improvement
Grant 6,982,433 - Hoffman , et al. January 3, 2
2006-01-03
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
App 20050224800 - Lindert, Nick ;   et al.
2005-10-13
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
App 20050218438 - Lindert, Nick ;   et al.
2005-10-06
Method of forming a shallow junction
Grant 6,936,505 - Keys , et al. August 30, 2
2005-08-30
Gate-induced strain for MOS performance improvement
App 20050167652 - Hoffmann, Thomas ;   et al.
2005-08-04
Transistor with strain-inducing structure in channel
App 20050106792 - Cea, Stephen M. ;   et al.
2005-05-19
High concentration indium fluorine retrograde wells
Grant 6,838,329 - Weber , et al. January 4, 2
2005-01-04
Gate-induced strain for MOS performance improvement
App 20040253776 - Hoffmann, Thomas ;   et al.
2004-12-16
Method of forming a shallow junction
App 20040235280 - Keys, Patrick H. ;   et al.
2004-11-25
High concentration indium fluorine retrograde wells
App 20040188767 - Weber, Cory E. ;   et al.
2004-09-30
High concentration indium fluorine retrograde wells
App 20040192055 - Weber, Cory E. ;   et al.
2004-09-30

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