Cea; Stephen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cea; Stephen.The latest application filed is for "transistor contact area enhancement".

Company Profile

9.4.18

Cea; Stephen - Hillsboro OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stacked nanowire transistor structure with different channel geometries for stress Grant 11,367,722 - Lilak , et al. June 21, 2	2022-06-21
Transistor Contact Area Enhancement App 20220157984 - MEHANDRU; Rishabh ; et al.	2022-05-19
Transistor contact area enhancement Grant 11,276,780 - Mehandru , et al. March 15, 2	2022-03-15
Multiple Strain States In Epitaxial Transistor Channel Through The Incorporation Of Stress-relief Defects Within An Underlying Seed Material App 20210257492 - Lilak; Aaron ; et al.	2021-08-19
Gate-all-around Integrated Circuit Structures Having Insulator Substrate App 20210202534 - LIN; Chung-Hsun ; et al.	2021-07-01
Removal Of A Bottom-most Nanowire From A Nanowire Device Stack App 20210159312 - Lilak; Aaron ; et al.	2021-05-27
Removal of a bottom-most nanowire from a nanowire device stack Grant 10,892,326 - Lilak , et al. January 12, 2	2021-01-12
Sub-fin Leakage Reduction For Template Strained Materials App 20200411640 - MEHANDRU; Rishabh ; et al.	2020-12-31
Deep Source & Drain For Transistor Structures With Back-side Contact Metallization App 20200303509 - MEHANDRU; Rishabh ; et al.	2020-09-24
Wrap-around Contact Structures For Semiconductor Nanowires And Nanoribbons App 20200219997 - MEHANDRU; Rishabh ; et al.	2020-07-09
Gate-all-around Integrated Circuit Structures Having Vertically Discrete Source Or Drain Structures App 20200105871 - GLASS; Glenn ; et al.	2020-04-02
Gate-all-around Integrated Circuit Structures Having High Mobility App 20200105753 - KOTLYAR; Roza ; et al.	2020-04-02
Stacked Nanowire Transistor Structure With Different Channel Geometries For Stress App 20200098756 - Lilak; Aaron ; et al.	2020-03-26
Channel Structures With Sub-fin Dopant Diffusion Blocking Layers App 20200006332 - BOMBERGER; Cory ; et al.	2020-01-02
Transistor Contact Area Enhancement App 20200006546 - MEHANDRU; Rishabh ; et al.	2020-01-02
Removal Of A Bottom-most Nanowire From A Nanowire Device Stack App 20190333990 - Lilak; Aaron ; et al.	2019-10-31
Spin Transfer Torque Memory And Logic Devices Having An Interface For Inducing A Strain On A Magnetic Layer Therein App 20170263853 - Manipatruni; Sasikanth ; et al.	2017-09-14
PMOS transistor strain optimization with raised junction regions App 20070034945 - Bohr; Mark T. ; et al.	2007-02-15
Integrated circuit with improved channel stress properties and a method for making it Grant 7,045,408 - Hoffmann , et al. May 16, 2	2006-05-16
PMOS transistor strain optimization with raised junction regions App 20040262683 - Bohr, Mark T. ; et al.	2004-12-30
Integrated circuit with improved channel stress properties and a method for making it App 20040235236 - Hoffmann, Thomas ; et al.	2004-11-25
Codoping of source drains using carbon or fluorine ion implants to improve polysilicon depletion App 20040102013 - Hwang, Jack ; et al.	2004-05-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.