Catherwood; Michael I.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Catherwood; Michael I..The latest application filed is for "programmable cpu register hardware context swap mechanism".
- Catherwood; Michael I. - Georgetown TX
- Catherwood; Michael I. - Pepperell MA
- Catherwood; Michael I. - Massachusetts MA
- Catherwood; Michael I. - Austin TX
| Patent | Date |
|---|---|
| Dual boot panel SWAP mechanism Grant 9,858,083 - Catherwood , et al. January 2, 2 | 2018-01-02 |
| Data space arbiter Grant 8,984,198 - Catherwood , et al. March 17, 2 | 2015-03-17 |
| Programmable CPU Register Hardware Context Swap Mechanism App 20150019847 - Catherwood; Michael I. ; et al. | 2015-01-15 |
| Dual Boot Panel SWAP Mechanism App 20140281465 - Catherwood; Michael I. ; et al. | 2014-09-18 |
| Programmable exception processing latency Grant 8,688,964 - Catherwood , et al. April 1, 2 | 2014-04-01 |
| DSP engine with implicit mixed sign operands Grant 8,495,125 - Catherwood , et al. July 23, 2 | 2013-07-23 |
| Register pointer trap to prevent errors due to an invalid pointer value in a register Grant 7,966,480 - Catherwood June 21, 2 | 2011-06-21 |
| Data Space Arbiter App 20110022756 - Catherwood; Michael I. ; et al. | 2011-01-27 |
| Programmable Exception Processing Latency App 20110016295 - Catherwood; Michael I. ; et al. | 2011-01-20 |
| DSP Engine with Implicit Mixed Sign Operands App 20100306292 - Catherwood; Michael I. ; et al. | 2010-12-02 |
| Dual mode arithmetic saturation processing Grant 7,467,178 - Catherwood December 16, 2 | 2008-12-16 |
| Reduced power option Grant 7,020,788 - Catherwood March 28, 2 | 2006-03-28 |
| Maximally negative signed fractional number multiplication Grant 6,952,711 - Catherwood October 4, 2 | 2005-10-04 |
| Euclidean distance instructions Grant 6,934,728 - Catherwood August 23, 2 | 2005-08-23 |
| Register pointer trap App 20050172109 - Catherwood, Michael I. | 2005-08-04 |
| Microcontroller instruction set App 20050166036 - Catherwood, Michael I. ; et al. | 2005-07-28 |
| Modulo addressing based on absolute offset Grant 6,604,169 - Catherwood August 5, 2 | 2003-08-05 |
| Reduced power option App 20030126484 - Catherwood, Michael I. | 2003-07-03 |
| Digital signal controller instruction set and architecture App 20030061464 - Catherwood, Michael I. ; et al. | 2003-03-27 |
| Compatible effective addressing with a dynamically reconfigurable data space word width App 20030005254 - Triece, Joseph W. ; et al. | 2003-01-02 |
| Multi-precision barrel shifting App 20030005269 - Conner, Joshua M. ; et al. | 2003-01-02 |
| Find first bit value instruction App 20030005268 - Catherwood, Michael I. | 2003-01-02 |
| Modulo addressing based on absolute offset App 20020194452 - Catherwood, Michael I. | 2002-12-19 |
| Euclidean distance instructions App 20020188639 - Catherwood, Michael I. | 2002-12-12 |
| Dual mode arithmetic saturation processing App 20020188640 - Catherwood, Michael I. | 2002-12-12 |
| Maximally negative signed fractional number multiplication App 20020184286 - Catherwood, Michael I. | 2002-12-05 |
| Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory Grant 5,890,191 - Espinor , et al. March 30, 1 | 1999-03-30 |
| Method and apparatus for determining wait states on a per cycle basis in a data processing system Grant 5,854,944 - Catherwood , et al. December 29, 1 | 1998-12-29 |
| Data processor having a timer circuit for performing a buffered pulse width modulation function and method therefor Grant 5,535,376 - Catherwood , et al. July 9, 1 | 1996-07-09 |
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