loadpatents
name:-0.016066074371338
name:-0.02482795715332
name:-0.010034084320068
Casey; Jon A. Patent Filings

Casey; Jon A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Casey; Jon A..The latest application filed is for "polygon integrated circuit (ic) packaging".

Company Profile
6.44.27
  • Casey; Jon A. - Poughkeepsie NY
  • Casey; Jon A. - Pooghkeepsie NY
  • Casey; Jon A - Poughkeepsie NY US
  • Casey; Jon A. - Poughhkeepsie NY
  • Casey; Jon A. - LaGrange NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Polygon integrated circuit (IC) packaging
Grant 11,410,894 - Arvin , et al. August 9, 2
2022-08-09
Direct bonded heterogeneous integration packaging structures
Grant 11,177,217 - Sikka , et al. November 16, 2
2021-11-16
Polygon Integrated Circuit (ic) Packaging
App 20210074599 - Arvin; Charles L. ;   et al.
2021-03-11
Electronic Device Console With Natural Draft Cooling
App 20210022239 - SIKKA; Kamal K. ;   et al.
2021-01-21
Electronic device console with natural draft cooling
Grant 10,834,808 - Bodenweber , et al. November 10, 2
2020-11-10
Direct Bonded Heterogeneous Integration Packaging Structures
App 20200144187 - Sikka; Kamal K. ;   et al.
2020-05-07
Direct bonded heterogeneous integration packaging structures
Grant 10,580,738 - Sikka , et al.
2020-03-03
Direct Bonded Heterogeneous Integration Packaging Structures
App 20190295952 - Sikka; Kamal K. ;   et al.
2019-09-26
Under die surface mounted electrical elements
Grant 9,601,423 - Arvin , et al. March 21, 2
2017-03-21
Managing interconnect electromigration effects
Grant 9,477,568 - Allen-Ware , et al. October 25, 2
2016-10-25
Electronic Device Console With Natural Draft Cooling
App 20160021731 - BODENWEBER; Paul F. ;   et al.
2016-01-21
Electronic device console with natural draft cooling
Grant 9,226,426 - Bodenweber , et al. December 29, 2
2015-12-29
Managing Interconnect Electromigration Effects
App 20150094995 - Allen-Ware; Malcolm S. ;   et al.
2015-04-02
Passivation layer surface topography modifications for improved integrity in packaged assemblies
Grant 8,786,059 - Blander , et al. July 22, 2
2014-07-22
Electronic Device Console With Natural Draft Cooling
App 20140024465 - BODENWEBER; Paul F. ;   et al.
2014-01-23
Achieving mechanical and thermal stability in a multi-chip package
Grant 8,421,217 - Casey , et al. April 16, 2
2013-04-16
Passivation Layer Surface Topography Modifications For Improved Integrity In Packaged Assemblies
App 20120228748 - BLANDER; ALEXANDRE ;   et al.
2012-09-13
Passivation layer surface topography modifications for improved integrity in packaged assemblies
Grant 8,236,615 - Blander , et al. August 7, 2
2012-08-07
System And Method Of Achieving Mechanical And Thermal Stability In A Multi-chip Package
App 20120175766 - Casey; Jon A. ;   et al.
2012-07-12
Enhanced thermal management for improved module reliability
Grant 8,214,658 - Casey , et al. July 3, 2
2012-07-03
Achieving mechanical and thermal stability in a multi-chip package
Grant 8,202,765 - Casey , et al. June 19, 2
2012-06-19
Passivation Layer Surface Topography Modifications For Improved Integrity In Packaged Assemblies
App 20110121469 - Blander; Alexandre ;   et al.
2011-05-26
Tracking thermal mini-cycle stress
Grant 7,917,328 - Casey , et al. March 29, 2
2011-03-29
System and Method of Achieving Mechanical and Thermal Stability in a Multi-Chip Package
App 20100181665 - CASEY; Jon A. ;   et al.
2010-07-22
Tracking Thermal Mini-Cycle Stress
App 20100049466 - Casey; Jon A. ;   et al.
2010-02-25
Enhanced Thermal Management for Improved Module Reliability
App 20100049995 - Casey; Jon A. ;   et al.
2010-02-25
Method and apparatus for filling vias
Grant 7,449,067 - Andry , et al. November 11, 2
2008-11-11
Enhanced via structure for organic module performance
Grant 7,312,523 - Audet , et al. December 25, 2
2007-12-25
Electronic package repair process
Grant 7,294,909 - Casey , et al. November 13, 2
2007-11-13
Suspension for filling via holes in silicon and method for making the same
Grant 7,288,474 - Casey , et al. October 30, 2
2007-10-30
Suspension for filling via holes in silicon and method for making the same
Grant 7,202,154 - Casey , et al. April 10, 2
2007-04-10
Materials and method to seal vias in silicon substrates
Grant 7,199,450 - Casey , et al. April 3, 2
2007-04-03
Suspension for filling via holes in silicon and method for making the same
App 20070032078 - Casey; Jon A. ;   et al.
2007-02-08
Enhanced Via Structure For Organic Module Performance
App 20070023913 - Audet; Jean J. ;   et al.
2007-02-01
Materials And Method To Seal Vias In Silicon Substrates
App 20060255480 - Casey; Jon A. ;   et al.
2006-11-16
Method for integrating thermistor
Grant 7,078,259 - Casey , et al. July 18, 2
2006-07-18
Low-K dielectric material system for IC application
Grant 7,015,581 - Casey , et al. March 21, 2
2006-03-21
Low-k dielectric material system for IC application
App 20050200025 - Casey, Jon A. ;   et al.
2005-09-15
Electronic package repair process
App 20050176255 - Casey, Jon A. ;   et al.
2005-08-11
Method And Structure For Integrating Thermistor
App 20050151213 - Casey, Jon A. ;   et al.
2005-07-14
Electronic package repair process
Grant 6,916,670 - Casey , et al. July 12, 2
2005-07-12
A Suspension For Filling Via Holes In Silicon And Method For Making The Same
App 20050148164 - CASEY, JON A. ;   et al.
2005-07-07
Method and apparatus for filling vias
App 20050106834 - Andry, Paul S. ;   et al.
2005-05-19
Low-k dielectric material system for IC application
Grant 6,878,616 - Casey , et al. April 12, 2
2005-04-12
Method of selective plating on a substrate
Grant 6,823,585 - LaPlante , et al. November 30, 2
2004-11-30
Selective plating using dual lift-off mask
App 20040187303 - LaPlante, Mark J. ;   et al.
2004-09-30
Electronic package repair process
App 20040148765 - Casey, Jon A. ;   et al.
2004-08-05
Method of joining laminates for z-axis interconnection
App 20030041966 - Casey, Jon A. ;   et al.
2003-03-06
Multi-level web structure in use for thin sheet processing
App 20020092600 - Natarajan, Govindarajan ;   et al.
2002-07-18
Process For Screening Features On An Electronic Substrate With A Low Viscosity Paste
App 20020009539 - CASEY, JON A. ;   et al.
2002-01-24
Thermoelectric devices and methods for making the same
Grant 6,278,049 - Johnson , et al. August 21, 2
2001-08-21
Thermoelectric devices and methods for making the same
Grant 6,262,357 - Johnson , et al. July 17, 2
2001-07-17
Thermoelectric devices and methods for making the same
Grant 6,121,539 - Johnson , et al. September 19, 2
2000-09-19
Process for via fill
Grant 5,927,193 - Balz , et al. July 27, 1
1999-07-27
Method of forming a multilayer electronic packaging substrate with integral cooling channels
Grant 5,870,823 - Bezama , et al. February 16, 1
1999-02-16
Method of using an interface layer for stacked lamination sizing and sintering
Grant 5,866,470 - Casey , et al. February 2, 1
1999-02-02
Method for making ceramic substrates from thin and thick ceramic greensheets
Grant 5,601,672 - Casey , et al. February 11, 1
1997-02-11
Aluminum nitride body having graded metallurgy
Grant 5,552,107 - Casey , et al. September 3, 1
1996-09-03
Aluminum nitride body having graded metallurgy
Grant 5,552,232 - Casey , et al. September 3, 1
1996-09-03
Large ceramic article and method of manufacturing
Grant 5,541,005 - Bezama , et al. July 30, 1
1996-07-30
Process for producing circuitized layers and multilayer ceramic sub-laminates and composites thereof
Grant 5,480,503 - Casey , et al. January 2, 1
1996-01-02
Toughened glass ceramic substrates for semiconductor devices subjected to oxidizing atmospheres during sintering
Grant 5,304,517 - Casey , et al. April 19, 1
1994-04-19
Process for fabricating a low dielectric composite substrate
Grant 5,277,725 - Acocella , et al. January 11, 1
1994-01-11
Phenyl-endcapped depolymerizable polymer
Grant 5,147,741 - Araps , et al. September 15, 1
1992-09-15
Low dielectric composite substrate
Grant 5,139,851 - Acocella , et al. August 18, 1
1992-08-18
Process for fabricating a low dielectric composite substrate
Grant 5,135,595 - Acocella , et al. August 4, 1
1992-08-04
Method of making multilayered ceramic structures having an internal distribution of copper-based conductors
Grant 4,885,038 - Anderson, Jr. , et al. December 5, 1
1989-12-05

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