CASARSA; Marco

Patent Applications and Registrations

Patent applications and USPTO patent grants for CASARSA; Marco.The latest application filed is for "scan chain circuit and corresponding method".

Company Profile

0.9.8

CASARSA; Marco - Milano IT
Casarsa; Marco - Vaprio D'Adda N/A IT
Casarsa; Marco - Milan IT
CASARSA; Marco - Vaprio d'adda - Milano IT
CASARSA; Marco - Vaprio d'Adda MI

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Scan Chain Circuit And Corresponding Method App 20220263499 - CASARSA; Marco	2022-08-18
System for performing the test of digital circuits Grant 8,996,939 - Casarsa March 31, 2	2015-03-31
Electrical interconnection integrated device with fault detecting module and electronic apparatus comprising the device Grant 8,618,812 - Casarsa December 31, 2	2013-12-31
Shared diagnosis method for an integrated electronic system including a plurality of memory units Grant 8,099,640 - Casarsa January 17, 2	2012-01-17
System For Performing The Test Of Digital Circuits App 20110258499 - Casarsa; Marco	2011-10-20
Electrical Interconnection Integrated Device With Fault Detecting Module And Electronic Apparatus Comprising The Device App 20110187384 - Casarsa; Marco	2011-08-04
Asynchronous set-reset circuit device Grant 7,941,715 - Casarsa May 10, 2	2011-05-10
Scan chain architecture for increased diagnostic capability in digital electronic devices Grant 7,900,103 - Casarsa March 1, 2	2011-03-01
Scan compression architecture for a design for testability compiler used in system-on-chip software design tools Grant 7,702,983 - Casarsa April 20, 2	2010-04-20
Shared Diagnosis Method For An Integrated Electronic System Including A Plurality Of Memory Units App 20100058128 - CASARSA; Marco	2010-03-04
Scan Chain Architecture For Increased Diagnostic Capability In Digital Electronic Devices App 20080155365 - Casarsa; Marco	2008-06-26
Asynchronous Set-reset Circuit Device App 20070300116 - CASARSA; Marco	2007-12-27
Scan Compression Architecture For A Design For Testability Compiler Used In System-on-chip Software Design Tools App 20070283200 - Casarsa; Marco	2007-12-06
Integrated device with an improved BIST circuit for executing a structured test Grant 7,246,288 - Casarsa July 17, 2	2007-07-17
Integrated device with an improved BIST circuit for executing a structured test App 20050034041 - Casarsa, Marco	2005-02-10

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