loadpatents
name:-0.016522169113159
name:-0.014904022216797
name:-0.00046014785766602
Casado; Javier Carretero Patent Filings

Casado; Javier Carretero

Patent Applications and Registrations

Patent applications and USPTO patent grants for Casado; Javier Carretero.The latest application filed is for "vulnerability estimation for cache memory".

Company Profile
0.20.20
  • Casado; Javier Carretero - Barcelona ES
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Capacity register file
Grant 10,020,037 - Abella , et al. July 10, 2
2018-07-10
Disabling cache portions during low voltage operations
Grant 9,678,878 - Wilkerson , et al. June 13, 2
2017-06-13
Traffic control on an on-chip network
Grant 9,608,922 - Monchiero , et al. March 28, 2
2017-03-28
Register error protection through binary translation
Grant 9,405,647 - Vera , et al. August 2, 2
2016-08-02
Recovering from data errors using implicit redundancy
Grant 9,170,947 - Vera , et al. October 27, 2
2015-10-27
Vulnerability estimation for cache memory
Grant 9,075,904 - Casado , et al. July 7, 2
2015-07-07
Selective provision of error correction for memory
Grant 9,071,281 - Casado , et al. June 30, 2
2015-06-30
Vulnerability Estimation For Cache Memory
App 20140281740 - Casado; Javier Carretero ;   et al.
2014-09-18
Selective Provision Of Error Correction For Memory
App 20140258805 - Casado; Javier Carretero ;   et al.
2014-09-11
Disabling Cache Portions During Low Voltage Operations
App 20140108733 - Wilkerson; Christopher ;   et al.
2014-04-17
Recovering From Data Errors Using Implicit Redundancy
App 20140089593 - Vera; Xavier ;   et al.
2014-03-27
Traffic Control On An On-chip Network
App 20140010079 - Monchiero; Matteo ;   et al.
2014-01-09
Register Error Protection Through Binary Translation
App 20130318401 - Vera; Xavier ;   et al.
2013-11-28
Memory apparatuses with low supply voltages
Grant 8,477,558 - Abella , et al. July 2, 2
2013-07-02
Protecting data storage structures from intermittent errors
Grant 8,352,812 - Vera , et al. January 8, 2
2013-01-08
Disabling cache portions during low voltage operations
Grant 8,291,168 - Wilkerson , et al. October 16, 2
2012-10-16
Disabling Cache Portions During Low Voltage Operations
App 20120110266 - Wilkerson; Christopher ;   et al.
2012-05-03
Disabling cache portions during low voltage operations
Grant 8,103,830 - Wilkerson , et al. January 24, 2
2012-01-24
On-line testing for decode logic
Grant 8,069,376 - Monferrer , et al. November 29, 2
2011-11-29
On-line Testing For Decode Logic
App 20100299507 - Monferrer; Pedro Chaparro ;   et al.
2010-11-25
Correcting intermittent errors in data storage structures
Grant 7,747,913 - Abella , et al. June 29, 2
2010-06-29
Memory Apparatuses With Low Supply Voltages
App 20100115224 - Abella; Jaume ;   et al.
2010-05-06
Disabling Cache Portions During Low Voltage Operations
App 20100082905 - Wilkerson; Christopher ;   et al.
2010-04-01
Memory content inverting to minimize NTBI effects
Grant 7,577,015 - Abella , et al. August 18, 2
2009-08-18
Mechanism for soft error detection and recovery in issue queues
App 20090150653 - Monferrer; Pedro Chaparro ;   et al.
2009-06-11
Capacity Register File
App 20090150649 - Abella; Jaume ;   et al.
2009-06-11
Correcting Intermittent Errors In Data Storage Structures
App 20090037781 - Abella; Jaume ;   et al.
2009-02-05
Protecting Data Storage Structures From Intermittent Errors
App 20090037783 - Vera; Xavier ;   et al.
2009-02-05
Memory content inverting to minimize NTBI effects
App 20080244182 - Abella; Jaume ;   et al.
2008-10-02

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