Carberry; Richard A.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Carberry; Richard A..The latest application filed is for "double data rate flip-flop".
- Carberry; Richard A. - Los Gatos CA
- Carberry; Richard A. - late of Los Gatos CA
- Carberry; Richard A. - Cupertino CA
| Patent | Date |
|---|---|
| Double data rate flip-flop Grant 7,317,773 - Young , et al. January 8, 2 | 2008-01-08 |
| Double data rate flip-flop App 20040239365 - Young, Steven P. ; et al. | 2004-12-02 |
| Double data rate flip-flop Grant 6,777,980 - Young , et al. August 17, 2 | 2004-08-17 |
| FPGA lookup table with high speed read decorder Grant 6,621,296 - Carberry , et al. September 16, 2 | 2003-09-16 |
| Double data rate flip-flop App 20030112032 - Young, Steven P. ; et al. | 2003-06-19 |
| FPGA lookup table with high speed read decoder App 20030071653 - Carberry, Richard A. ; et al. | 2003-04-17 |
| FPGA lookup table with speed read decoder Grant 6,529,040 - Carberry , et al. March 4, 2 | 2003-03-04 |
| Double data rate flip-flop Grant 6,525,565 - Young , et al. February 25, 2 | 2003-02-25 |
| Logic/memory circuit having a plurality of operating modes Grant 6,501,296 - Wittig , et al. December 31, 2 | 2002-12-31 |
| Double data rate flip-flop App 20020175704 - Young, Steven P. ; et al. | 2002-11-28 |
| Method of time multiplexing a programmable logic device Grant 6,480,954 - Trimberger , et al. November 12, 2 | 2002-11-12 |
| FPGA lookup table with dual ended writes for ram and shift register modes Grant 6,373,279 - Bauer , et al. April 16, 2 | 2002-04-16 |
| Method of time multiplexing a programmable logic device App 20020010853 - Trimberger, Stephen M. ; et al. | 2002-01-24 |
| Logic/memory circuit having a plurality of operating modes App 20010043082 - Wittig, Ralph D. ; et al. | 2001-11-22 |
| Programmable logic device having configurable logic blocks with user-accessible input multiplexers Grant 6,292,019 - New , et al. September 18, 2 | 2001-09-18 |
| Method of time multiplexing a programmable logic device Grant 6,263,430 - Trimberger , et al. July 17, 2 | 2001-07-17 |
| FPGA configurable logic block with multi-purpose logic/memory circuit Grant 6,150,838 - Wittig , et al. November 21, 2 | 2000-11-21 |
| Delay control circuit using dynamic latches Grant 6,078,528 - Johnson , et al. June 20, 2 | 2000-06-20 |
| Method of time multiplexing a programmable logic device Grant 5,978,260 - Trimberger , et al. November 2, 1 | 1999-11-02 |
| Programmable logic device including configuration data or user data memory slices Grant 5,959,881 - Trimberger , et al. September 28, 1 | 1999-09-28 |
| Programmable logic device including configuration data or user data memory slices Grant 5,784,313 - Trimberger , et al. July 21, 1 | 1998-07-21 |
| Programmable logic device with hierarchical confiquration and state storage Grant 5,778,439 - Trimberger , et al. July 7, 1 | 1998-07-07 |
| Time multiplexed programmable logic device Grant 5,646,545 - Trimberger , et al. July 8, 1 | 1997-07-08 |
| Method of time multiplexing a programmable logic device Grant 5,629,637 - Trimberger , et al. May 13, 1 | 1997-05-13 |
| Configuration modes for a time multiplexed programmable logic device Grant 5,600,263 - Trimberger , et al. February 4, 1 | 1997-02-04 |
| Sequencer for a time multiplexed programmable logic device Grant 5,583,450 - Trimberger , et al. December 10, 1 | 1996-12-10 |
| Input synchronization mechanism for inside/outside clock Grant 5,578,946 - Carberry , et al. November 26, 1 | 1996-11-26 |
| Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit Grant 4,794,524 - Carberry , et al. December 27, 1 | 1988-12-27 |
| Data processing system utilizing a unique two-level microcoding technique for forming microinstructions Grant 4,394,736 - Bernstein , et al. July 19, 1 | 1983-07-19 |
| Data processing system having unique bus control operation Grant 4,371,925 - Carberry , et al. February 1, 1 | 1983-02-01 |
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