Caprara; Paolo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Caprara; Paolo.The latest application filed is for "mos device and a process for manufacturing mos devices using a dual-polysilicon layer technology with side contact".

Company Profile

0.10.7

Caprara; Paolo - Milan IT
Caprara; Paolo - Milano IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell Grant 7,319,604 - Khouri , et al. January 15, 2	2008-01-15
MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact App 20060246646 - Caimi; Carlo ; et al.	2006-11-02
Process for manufacturing a dual charge storage location memory cell Grant 7,115,472 - Caprara , et al. October 3, 2	2006-10-03
MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact Grant 7,091,570 - Caimi , et al. August 15, 2	2006-08-15
Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell App 20060158931 - Khouri; Osama ; et al.	2006-07-20
MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology Grant 7,023,047 - Tessa Contin , et al. April 4, 2	2006-04-04
MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact App 20050116288 - Caimi, Carlo ; et al.	2005-06-02
Process for manufacturing a dual charge storage location memory cell App 20050064654 - Caprara, Paolo ; et al.	2005-03-24
Process for manufacturing a dual charge storage location memory cell Grant 6,825,523 - Caprara , et al. November 30, 2	2004-11-30
MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology App 20040188759 - Contin, Valentina Tessa ; et al.	2004-09-30
Multi-emitter bipolar transistor for bandgap reference circuits Grant 6,700,226 - Vendrame , et al. March 2, 2	2004-03-02
Process for manufacturing a dual charge storage location memory cell App 20030067032 - Caprara, Paolo ; et al.	2003-04-10
Multi-emitter bipolar transistor for bandgap reference circuits App 20020149089 - Vendrame, Loris ; et al.	2002-10-17
Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground Grant 6,365,456 - Cereda , et al. April 2, 2	2002-04-02
Method of manufacturing an EPROM memory device having memory cells organized in a tablecloth matrix Grant 6,326,266 - Brambilla , et al. December 4, 2	2001-12-04
Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arrays Grant 6,251,736 - Brambilla , et al. June 26, 2	2001-06-26
Method for manufacturing a native MOS P-channel transistor with a process for manufacturing non-volatile memories Grant 6,063,663 - Caprara , et al. May 16, 2	2000-05-16

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