CAPPELLETTI; Paolo Giuseppe

Patent Applications and Registrations

Patent applications and USPTO patent grants for CAPPELLETTI; Paolo Giuseppe.The latest application filed is for "memory device".

Company Profile

3.12.12

CAPPELLETTI; Paolo Giuseppe - Seveso MI
Cappelletti; Paolo Giuseppe - Seveso IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory Device App 20220302379 - CAPPELLETTI; Paolo Giuseppe ; et al.	2022-09-22
Switching Cell App 20220238603 - CAPPELLETTI; Paolo Giuseppe ; et al.	2022-07-28
Memory device Grant 11,355,702 - Cappelletti , et al. June 7, 2	2022-06-07
Memory cell Grant 11,227,992 - Cappelletti January 18, 2	2022-01-18
Phase-change Memory Cell App 20210249594 - CAPPELLETTI; Paolo Giuseppe ; et al.	2021-08-12
Memory device Grant 10,910,558 - Cappelletti , et al. February 2, 2	2021-02-02
Memory Cell App 20200381618 - CAPPELLETTI; Paolo Giuseppe	2020-12-03
Memory Device App 20200052199 - CAPPELLETTI; Paolo Giuseppe ; et al.	2020-02-13
Memory Device App 20200052198 - CAPPELLETTI; Paolo Giuseppe ; et al.	2020-02-13
Semiconductor constructions and methods of forming memory cells Grant 9,577,188 - Cupeta , et al. February 21, 2	2017-02-21
Semiconductor Constructions and Methods of Forming Memory Cells App 20160056375 - Cupeta; Carmela ; et al.	2016-02-25
Semiconductor constructions and methods of forming memory cells Grant 9,166,159 - Cupeta , et al. October 20, 2	2015-10-20
Semiconductor Constructions and Methods of Forming Memory Cells App 20140346429 - Cupeta; Carmela ; et al.	2014-11-27
Transistor structure with high input impedance and high current capability Grant 7,560,782 - Pellizzer , et al. July 14, 2	2009-07-14
Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit Grant 7,320,904 - Cappelletti , et al. January 22, 2	2008-01-22
Transistor structure with high input impedance and high current capability and manufacturing process thereof App 20070126064 - Pellizzer; Fabio ; et al.	2007-06-07
Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit App 20060189136 - Cappelletti; Paolo Giuseppe ; et al.	2006-08-24
Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit Grant 7,001,800 - Cappelletti , et al. February 21, 2	2006-02-21
Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit App 20050032278 - Cappelletti, Paolo Giuseppe ; et al.	2005-02-10
Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry Grant 6,713,347 - Cappelletti , et al. March 30, 2	2004-03-30
Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry App 20020140047 - Cappelletti, Paolo Giuseppe ; et al.	2002-10-03
Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry Grant 6,410,387 - Cappelletti , et al. June 25, 2	2002-06-25
Process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection Grant 5,913,120 - Cappelletti June 15, 1	1999-06-15
Method for evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories Grant 5,712,816 - Cappelletti , et al. January 27, 1	1998-01-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.