Cappellano; Ivana
Patent Applications and Registrations
Patent applications and USPTO patent grants for Cappellano; Ivana.The latest application filed is for "glitch free programmable delay line for edge sensitive design".
- Cappellano; Ivana - Palermo IT
- Cappellano, Ivana - US
| Patent | Date |
|---|---|
| Cascode stage input/output device Grant 6,906,561 - Yu , et al. June 14, 2 | 2005-06-14 |
| Glitch free programmable delay line for edge sensitive design App 20040225976 - Cheung, Daniel Y. ; et al. | 2004-11-11 |
| Method and circuitry for phase align detection in multi-clock domain App 20040100308 - Sutera, Massimo ; et al. | 2004-05-27 |
| Output driver having dynamic impedance control Grant 6,700,418 - Yu , et al. March 2, 2 | 2004-03-02 |
| Output Driver Having Dynamic Impedance Control App 20030222683 - Yu, Shifeng Jack ; et al. | 2003-12-04 |
| Cascode stage input/output device App 20030222682 - Yu, Shifeng Jack ; et al. | 2003-12-04 |
| Input/output device having linearized output response App 20030225943 - Yu, Shifeng Jack ; et al. | 2003-12-04 |
| Input/output device having dynamic delay Grant 6,600,348 - Yu , et al. July 29, 2 | 2003-07-29 |
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