loadpatents
name:-0.022421836853027
name:-0.050344944000244
name:-0.00050806999206543
CAPODIECI; Luigi Patent Filings

CAPODIECI; Luigi

Patent Applications and Registrations

Patent applications and USPTO patent grants for CAPODIECI; Luigi.The latest application filed is for "pattern matching for predicting defect limited yield".

Company Profile
0.47.21
  • CAPODIECI; Luigi - Santa Cruz CA
  • Capodieci; Luigi - San Cruz CA
  • Capodieci; Luigi - Sunnyvale CA
  • Capodieci; Luigi - Madison WI
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Pattern Matching For Predicting Defect Limited Yield
App 20150286763 - WANG; Lynn ;   et al.
2015-10-08
Automated design layout pattern correction based on context-aware patterns
Grant 8,924,896 - Wang , et al. December 30, 2
2014-12-30
Stitch insertion for reducing color density differences in double patterning technology (DPT)
Grant 8,918,745 - Wang , et al. December 23, 2
2014-12-23
Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
Grant 8,910,090 - Wang , et al. December 9, 2
2014-12-09
Layout pattern correction for integrated circuits
Grant 8,898,606 - Abou Ghaida , et al. November 25, 2
2014-11-25
Stitch Insertion For Reducing Color Density Differences In Double Patterning Technology (dpt)
App 20140282301 - WANG; Lynn ;   et al.
2014-09-18
Methods Involving Pattern Matching To Identify And Resolve Potential Non-double-patterning-compliant Patterns In Double Patterning Applications
App 20140245238 - Wang; Lynn T. ;   et al.
2014-08-28
Automated Design Layout Pattern Correction Based On Context-aware Patterns
App 20140215415 - WANG; Lynn ;   et al.
2014-07-31
Methods for analyzing design rules
Grant 8,589,844 - Muddu , et al. November 19, 2
2013-11-19
Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns
Grant 8,555,215 - Zou , et al. October 8, 2
2013-10-08
Methods For Decomposing Circuit Design Layouts And For Fabricating Semiconductor Devices Using Decomposed Patterns
App 20130219347 - Zou; Yi ;   et al.
2013-08-22
Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts
Grant 8,516,407 - Wang , et al. August 20, 2
2013-08-20
Methods For Analyzing Design Rules
App 20130212548 - Muddu; Swamy ;   et al.
2013-08-15
Methods For Quantitatively Evaluating The Quality Of Double Patterning Technology-compliant Layouts
App 20130198696 - Wang; Lynn T. ;   et al.
2013-08-01
Methods for pattern matching in a double patterning technology-compliant physical design flow
Grant 8,418,105 - Wang , et al. April 9, 2
2013-04-09
Method of lithographic mask correction using localized transmission adjustment
Grant 8,124,300 - Singh , et al. February 28, 2
2012-02-28
System for generating and optimizing mask assist features based on hybrid (model and rules) methodology
Grant 8,103,979 - Zou , et al. January 24, 2
2012-01-24
Single/double dipole mask for contact holes
Grant 7,799,517 - Capodieci September 21, 2
2010-09-21
Design rules checking augmented with pattern matching
Grant 7,757,190 - Dai , et al. July 13, 2
2010-07-13
System For Generating And Optimizing Mask Assist Features Based On Hybrid (model And Rules) Methodology
App 20100099032 - Zou; Yi ;   et al.
2010-04-22
System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
Grant 7,657,864 - Tabery , et al. February 2, 2
2010-02-02
Method And Apparatus For Monitoring Optical Proximity Correction Performance
App 20090144692 - CAIN; JASON P. ;   et al.
2009-06-04
Method And Apparatus For Monitoring Marginal Layout Design Rules
App 20090144686 - LENSING; KEVIN R. ;   et al.
2009-06-04
System and method for designing an integrated circuit device
Grant 7,543,256 - Lukanc , et al. June 2, 2
2009-06-02
Design Rules Checking Augmented With Pattern Matching
App 20080148211 - Dai; Vito ;   et al.
2008-06-19
Chromeless mask for contact holes
Grant 7,354,682 - Capodieci April 8, 2
2008-04-08
Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
Grant 7,313,769 - Lukanc , et al. December 25, 2
2007-12-25
Layout verification based on probability of printing fault
Grant 7,313,777 - Yang , et al. December 25, 2
2007-12-25
Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures
Grant 7,310,155 - Capodieci , et al. December 18, 2
2007-12-18
Method for manufacturing place & route based on 2-D forbidden patterns
Grant 7,305,645 - Capodieci , et al. December 4, 2
2007-12-04
System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
Grant 7,269,804 - Tabery , et al. September 11, 2
2007-09-11
System And Method For Integrated Circuit Device Design And Manufacture Using Optical Rule Checking To Screen Resolution Enhancement Techniques
App 20070209030 - Tabery; Cyrus E. ;   et al.
2007-09-06
Simplified optical proximity correction based on 1-dimension versus 2-dimension pattern shape classification
Grant 7,263,683 - Capodieci August 28, 2
2007-08-28
Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results
Grant 7,207,017 - Tabery , et al. April 17, 2
2007-04-17
System and method for design rule creation and selection
Grant 7,194,725 - Lukanc , et al. March 20, 2
2007-03-20
Method of developing optimized optical proximity correction (OPC) fragmentation script for photolithographic processing
Grant 7,080,349 - Babcock , et al. July 18, 2
2006-07-18
Predefined critical spaces in IC patterning to reduce line end pull back
Grant 7,071,085 - Lukanc , et al. July 4, 2
2006-07-04
Device and method for determining an illumination intensity profile of an illuminator for a lithography system
Grant 7,027,130 - Spence , et al. April 11, 2
2006-04-11
Reduce line end pull back by exposing and etching space after mask one trim and etch
Grant 7,015,148 - Lukanc , et al. March 21, 2
2006-03-21
Microdevice having non-linear structural component and method of fabrication
Grant 6,995,433 - Lukanc , et al. February 7, 2
2006-02-07
Optical proximity correction (OPC) technique using generalized figure of merit for photolithograhic processing
Grant 6,978,438 - Capodieci December 20, 2
2005-12-20
Lithographic photomask and method of manufacture to improve photomask test measurement
Grant 6,974,652 - Lukanc , et al. December 13, 2
2005-12-13
Device and method for determining an illumination intensity profile of an illuminator for a lithography system
App 20050243299 - Spence, Christopher A. ;   et al.
2005-11-03
System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
App 20050229125 - Tabery, Cyrus E. ;   et al.
2005-10-13
Microdevice fabrication method using regular arrays of lines and spaces
Grant 6,583,041 - Capodieci June 24, 2
2003-06-24
Utilizing electrical performance data to predict CD variations across stepper field
Grant 6,562,639 - Minvielle , et al. May 13, 2
2003-05-13
Method and apparatus for generating masks utilized in conjunction with dipole illumination techniques
Grant 6,553,562 - Capodieci , et al. April 22, 2
2003-04-22
Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion
Grant 6,492,066 - Capodieci , et al. December 10, 2
2002-12-10
Method and apparatus for generating masks utilized in conjunction with dipole illumination techniques
App 20020166107 - Capodieci, Luigi ;   et al.
2002-11-07
Etch bias distribution across semiconductor wafer
App 20010031506 - Plat, Marina V. ;   et al.
2001-10-18
Methodology for extracting effective lens aberrations using a neural network
Grant 6,272,392 - Capodieci August 7, 2
2001-08-07
Etch bias distribution across semiconductor wafer
Grant 6,262,435 - Plat , et al. July 17, 2
2001-07-17
Mask quality measurements by fourier space analysis
Grant 6,187,483 - Capodieci , et al. February 13, 2
2001-02-13
Illumination modification scheme synthesis using lens characterization data
Grant 6,115,108 - Capodieci September 5, 2
2000-09-05
Modification of mask layout data to improve writeability of OPC
Grant 6,044,007 - Capodieci March 28, 2
2000-03-28
Fabrication of chrome/phase grating phase shift mask by interferometric lithography
Grant 6,013,396 - Capodieci January 11, 2
2000-01-11
Post-exposure bake simulator for chemically amplified photoresists
Grant 5,717,612 - Capodieci February 10, 1
1998-02-10

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