Caparas; Jose A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Caparas; Jose A..The latest application filed is for "semiconductor device and method of forming double-sided fan-out wafer level package".

Company Profile

2.18.15

Caparas; Jose A. - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device and method of forming double-sided fan-out wafer level package Grant 11,127,668 - Shim , et al. September 21, 2	2021-09-21
Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLB-MLP) Grant 10,622,293 - Yoon , et al.	2020-04-14
Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package App 20200006215 - Shim; Il Kwon ; et al.	2020-01-02
Semiconductor device and method of forming double-sided fan-out wafer level package Grant 10,453,785 - Shim , et al. Oc	2019-10-22
Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLP Grant 10,446,523 - Marimuthu , et al. Oc	2019-10-15
Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP App 20160336299 - Marimuthu; Pandi C. ; et al.	2016-11-17
Semiconductor device having wire studs as vertical interconnect in FO-WLP Grant 9,443,797 - Marimuthu , et al. September 13, 2	2016-09-13
Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLB-MLP) App 20160141238 - Yoon; Seung Wook ; et al.	2016-05-19
Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP) Grant 9,293,401 - Yoon , et al. March 22, 2	2016-03-22
Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package App 20160043047 - Shim; Il Kwon ; et al.	2016-02-11
Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die Grant 9,153,544 - Pagaila , et al. October 6, 2	2015-10-06
Semiconductor device and method of forming FO-WLCSP with multiple encapsulants Grant 9,142,428 - Lin , et al. September 22, 2	2015-09-22
Semiconductor device and method of making TSV interconnect structures using encapsulant for structural support Grant 9,054,083 - Suthiwongsunthorn , et al. June 9, 2	2015-06-09
Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die App 20140175623 - Pagaila; Reza A. ; et al.	2014-06-26
Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die Grant 8,710,635 - Pagaila , et al. April 29, 2	2014-04-29
Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support App 20140110861 - Suthiwongsunthorn; Nathapong ; et al.	2014-04-24
Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants App 20140077381 - Lin; Yaojian ; et al.	2014-03-20
Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP App 20140077364 - Marimuthu; Pandi C. ; et al.	2014-03-20
Semiconductor device having an interconnect structure with TSV using encapsulant for structural support Grant 8,659,162 - Suthiwongsunthorn , et al. February 25, 2	2014-02-25
Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLP-MLP) App 20130228917 - Yoon; Seung Wook ; et al.	2013-09-05
Wirebondless wafer level package with plated bumps and interconnects Grant 8,502,376 - Camacho , et al. August 6, 2	2013-08-06
Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die App 20120292749 - Pagaila; Reza A. ; et al.	2012-11-22
Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die Grant 8,258,012 - Pagaila , et al. September 4, 2	2012-09-04
Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support App 20120013004 - Suthiwongsunthorn; Nathapong ; et al.	2012-01-19
Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support Grant 8,067,308 - Suthiwongsunthorn , et al. November 29, 2	2011-11-29
Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die App 20110278703 - Pagaila; Reza A. ; et al.	2011-11-17
Wirebondless Wafer Level Package with Plated Bumps and Interconnects App 20110204512 - Camacho; Zigmund R. ; et al.	2011-08-25
Wirebondless wafer level package with plated bumps and interconnects Grant 7,964,450 - Camacho , et al. June 21, 2	2011-06-21
Semiconductor Device and Method of Forming an Interconnect Structure with TSV Using Encapsulant for Structural Support App 20100308443 - Suthiwongsunthorn; Nathapong ; et al.	2010-12-09
Wirebondless Wafer Level Package with Plated Bumps and Interconnects App 20090289356 - Camacho; Zigmund R. ; et al.	2009-11-26

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