CANO; Francisco A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for CANO; Francisco A..The latest application filed is for "stress reduction on stacked transistor circuits".

Company Profile

2.8.4

CANO; Francisco A. - Sugar Land TX
Cano; Francisco A. - Missouri City TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stress Reduction On Stacked Transistor Circuits App 20190326909 - BILHAN; Erkan ; et al.	2019-10-24
Stress Reduction On Stacked Transistor Circuits App 20190326910 - BILHAN; Erkan ; et al.	2019-10-24
Compensatory memory system Grant 8,144,533 - Cano March 27, 2	2012-03-27
Compensatory Memory System App 20100265779 - Cano; Francisco A.	2010-10-21
Method for power routing and distribution in an integrated circuit with multiple interconnect layers Grant 6,581,201 - Cano , et al. June 17, 2	2003-06-17
Method and apparatus for altering timing relationships of non-overlapping clock signals in a microprocessor Grant 6,381,704 - Cano , et al. April 30, 2	2002-04-30
Method for hierarchical parasitic extraction of a CMOS design Grant 6,363,516 - Cano , et al. March 26, 2	2002-03-26
Method for power routing and distribution in an integrated circuit with multiple interconnect layers App 20020013931 - Cano, Francisco A. ; et al.	2002-01-31
Method for analyzing circuit delays caused by capacitive coupling in digital circuits Grant 6,253,359 - Cano , et al. June 26, 2	2001-06-26
Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability Grant 6,038,383 - Young , et al. March 14, 2	2000-03-14
Method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory Grant 5,835,421 - Pham , et al. November 10, 1	1998-11-10
Method and apparatus for self-timed precharge of bit lines in a memory Grant 5,745,421 - Pham , et al. April 28, 1	1998-04-28

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