loadpatents
name:-0.014155149459839
name:-0.042248010635376
name:-0.0049269199371338
Camarota; Rafael C. Patent Filings

Camarota; Rafael C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Camarota; Rafael C..The latest application filed is for "unified programmable computational memory and configuration network".

Company Profile
5.43.13
  • Camarota; Rafael C. - San Jose CA
  • Camarota; Rafael C. - Sunnyvale CA
  • Camarota, Rafael C. - Sunnvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Unified programmable computational memory and configuration network
Grant 11,201,623 - Camarota December 14, 2
2021-12-14
Multi-rank high bandwidth memory (HBM) memory
Grant 11,189,338 - Camarota November 30, 2
2021-11-30
Configuring programmable logic region via programmable network
Grant 11,169,822 - Camarota , et al. November 9, 2
2021-11-09
Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture
Grant 10,963,411 - Voogel , et al. March 30, 2
2021-03-30
Layered boundary interconnect
Grant 10,929,331 - Camarota February 23, 2
2021-02-23
Unified Programmable Computational Memory And Configuration Network
App 20210050853 - CAMAROTA; Rafael C.
2021-02-18
Standalone interface for stacked silicon interconnect (SSI) technology integration
Grant 10,784,121 - Camarota Sept
2020-09-22
Boundary logic interface
Grant 10,763,862 - Camarota , et al. Sep
2020-09-01
Boundary Logic Interface
App 20200274536 - Camarota; Rafael C. ;   et al.
2020-08-27
Configuring Programmable Logic Region Via Programmable Network
App 20200264901 - Camarota; Rafael C. ;   et al.
2020-08-20
Unified programmable computational memory and configuration network
Grant 10,673,440 - Camarota
2020-06-02
Auto address generation for switch network
Grant 10,621,132 - Camarota , et al.
2020-04-14
Test network for a network on a chip and a configuration network
Grant 10,502,785 - Camarota Dec
2019-12-10
Heterogeneous ball pattern package
Grant 10,177,107 - Camarota J
2019-01-08
Circuit for and method of implementing a scan chain in programmable resources of an integrated circuit
Grant 10,069,497 - Devlin , et al. September 4, 2
2018-09-04
High bandwidth memory (HBM) bandwidth aggregation switch
Grant 9,911,465 - Camarota , et al. March 6, 2
2018-03-06
Standalone Interface For Stacked Silicon Interconnect (ssi) Technology Integration
App 20180047663 - Camarota; Rafael C.
2018-02-15
Heterogeneous Ball Pattern Package
App 20180033753 - Camarota; Rafael C.
2018-02-01
Rotated integrated circuit die and chip packages having the same
Grant 9,882,562 - Voogel , et al. January 30, 2
2018-01-30
Circuit For And Method Of Implementing A Scan Chain In Programmable Resources Of An Integrated Circuit
App 20170373692 - Devlin; Benjamin S. ;   et al.
2017-12-28
Monolithic integrated circuit die having modular die regions stitched together
Grant 9,547,034 - Camarota January 17, 2
2017-01-17
Multi-use package substrate
Grant 9,204,542 - Lee , et al. December 1, 2
2015-12-01
Memory matrix
Grant 9,083,340 - Wu , et al. July 14, 2
2015-07-14
Flexible sized die for use in multi-die integrated circuit
Grant 9,026,872 - Camarota May 5, 2
2015-05-05
Monolithic Integrated Circuit Die Having Modular Die Regions Stitched Together
App 20150008954 - Camarota; Rafael C.
2015-01-08
Dual port memory cell
Grant 8,913,455 - Camarota December 16, 2
2014-12-16
Oversized interposer formed from a multi-pattern region mask
Grant 8,869,088 - Camarota October 21, 2
2014-10-21
Predicting performance of an integrated circuit
Grant 8,712,718 - Camarota , et al. April 29, 2
2014-04-29
Flexible Sized Die For Use In Multi-die Integrated Circuit
App 20140049932 - Camarota; Rafael C.
2014-02-20
Method and apparatus for self-annealing multi-die interconnect redundancy control
Grant 8,539,420 - Camarota September 17, 2
2013-09-17
Method And Apparatus For Self-annealing Multi-die Interconnect Redundancy Control
App 20130009694 - Camarota; Rafael C.
2013-01-10
Method and system for using boundary scan in a programmable logic device
Grant 7,550,995 - Guilloteau , et al. June 23, 2
2009-06-23
Programmable logic device with on-chip nonvolatile user memory
Grant 7,550,994 - Camarota , et al. June 23, 2
2009-06-23
Input buffer with selectable threshold and hysteresis option
Grant 7,276,935 - Camarota October 2, 2
2007-10-02
Method and system for using boundary scan in a programmable logic device
Grant 7,248,070 - Guilloteau , et al. July 24, 2
2007-07-24
Programmable logic device with on-chip nonvolatile user memory
Grant 7,190,190 - Camarota , et al. March 13, 2
2007-03-13
Programmable logic with programmable volatility
Grant 7,154,297 - Camarota , et al. December 26, 2
2006-12-26
Input buffer with selectable threshold and hysteresis option
Grant 7,023,238 - Camarota April 4, 2
2006-04-04
Apparatus and method for self testing programmable logic arrays
App 20050039098 - Camarota, Rafael C.
2005-02-17
Programmable logic core adapter
Grant 6,744,274 - Arnold , et al. June 1, 2
2004-06-01
Efficient and robust random access memory cell suitable for programmable logic configuration control
Grant 6,418,045 - Camarota July 9, 2
2002-07-09
Built-in self test for a programmable logic device using linear feedback shift registers and hierarchical signature generation
App 20020078412 - Wang, Yongjiang ;   et al.
2002-06-20
Efficient and robust random access memory cell suitable for programmable logic configuration control
App 20020001222 - Camarota, Rafael C.
2002-01-03
Non-disruptive, randomly addressable memory system
Grant 5,488,582 - Camarota January 30, 1
1996-01-30
High performance output buffer with reduced ground bounce
Grant 5,341,040 - Garverick , et al. August 23, 1
1994-08-23
Configuration features in a configurable logic array
Grant 5,336,950 - Popli , et al. August 9, 1
1994-08-09
Dynamic three-state bussing capability in a configurable logic array
Grant 5,317,209 - Garverick , et al. May 31, 1
1994-05-31
Versatile and efficient cell-to-local bus interface in a configurable logic array
Grant 5,298,805 - Garverick , et al. March 29, 1
1994-03-29
Versatile programmable logic cell for use in configurable logic arrays
Grant 5,245,227 - Furtek , et al. September 14, 1
1993-09-14
Programmable logic cell and array with bus repeaters
Grant 5,218,240 - Camarota , et al. June 8, 1
1993-06-08
Programmable logic cell and array
Grant 5,144,166 - Camarota , et al. September 1, 1
1992-09-01

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