Callegari; Alessandro

Patent Applications and Registrations

Patent applications and USPTO patent grants for Callegari; Alessandro.The latest application filed is for "dielectric equivalent thickness and capacitance scaling for semiconductor devices".

Company Profile

0.11.9

Callegari; Alessandro - Yorktown Heights NY US
Callegari; Alessandro - Treviso IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method to improve nucleation of materials on graphene and carbon nanotubes Grant 8,895,352 - Babich , et al. November 25, 2	2014-11-25
Method to improve nucleation of materials on graphene and carbon nanotubes Grant 8,816,333 - Babich , et al. August 26, 2	2014-08-26
Dielectric equivalent thickness and capacitance scaling for semiconductor devices Grant 8,772,116 - Callegari , et al. July 8, 2	2014-07-08
Dielectric Equivalent Thickness And Capacitance Scaling For Semiconductor Devices App 20140138781 - CALLEGARI; Alessandro ; et al.	2014-05-22
Field-effect transistor device having a metal gate stack with an oxygen barrier layer Grant 8,415,677 - Adusumilli , et al. April 9, 2	2013-04-09
Method to Improve Nucleation of Materials on Graphene and Carbon Nanotubes App 20120235119 - Babich; Katherina ; et al.	2012-09-20
Field-effect Transistor Device Having A Metal Gate Stack With An Oxygen Barrier Layer App 20110175147 - Adusumilli; Praneet ; et al.	2011-07-21
Method to Improve Nucleation of Materials on Graphene and Carbon Nanotubes App 20100301336 - Babich; Katherina ; et al.	2010-12-02
Digital Memory Device Imbedded In The Temple Pieces Of Eyewear App 20100296045 - Agnoli; Giancarla ; et al.	2010-11-25
Formation of ultra-thin oxide layers by self-limiting interfacial oxidation Grant 7,235,440 - O'Meara , et al. June 26, 2	2007-06-26
Method of forming uniform ultra-thin oxynitride layers Grant 7,202,186 - O'Meara , et al. April 10, 2	2007-04-10
Interfacial oxidation process for high-k gate dielectric process integration Grant 6,974,779 - O'Meara , et al. December 13, 2	2005-12-13
Interfacial oxidation process for high-k gate dielectric process integration App 20050059259 - O'Meara, David L. ; et al.	2005-03-17
Formation of ultra-thin oxide layers by self-limiting interfacial oxidation App 20050026453 - O'Meara, David L. ; et al.	2005-02-03
Method of forming uniform ultra-thin oxynitride layers App 20050026459 - O'Meara, David L. ; et al.	2005-02-03
Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation Grant 6,759,321 - Babich , et al. July 6, 2	2004-07-06
Stabilization Of Fluorine-containing Low-k Dielectrics In A Metal/insulator Wiring Structure By Ultraviolet Irradiation App 20020033535 - BABICH, KATHERINA ; et al.	2002-03-21

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.