Calder; Iain D.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Calder; Iain D..The latest application filed is for "method of making a capacitor for an integrated circuit".
- Calder; Iain D. - Kanata CA
- Calder; Iain D. - Nepean CA
| Patent | Date |
|---|---|
| Method of making a capacitor for an integrated circuit Grant 5,330,931 - Emesh , et al. July 19, 1 | 1994-07-19 |
| Silicon-on-insulator substrates annealed in polysilicon tube Grant 4,804,633 - Macelwee , et al. February 14, 1 | 1989-02-14 |
| Process of fabricating MOS devices having shallow source and drain junctions Grant 4,683,645 - Naguib , et al. August 4, 1 | 1987-08-04 |
| Structure and fabrication of vertically integrated CMOS logic gates Grant 4,680,609 - Calder , et al. July 14, 1 | 1987-07-14 |
| Laser activated polysilicon connections for redundancy Grant 4,561,906 - Calder , et al. December 31, 1 | 1985-12-31 |
| Interactive viewgraph system Grant 4,503,468 - Serinken , et al. March 5, 1 | 1985-03-05 |
| Stacked MOS transistor Grant 4,476,475 - Naem , et al. October 9, 1 | 1984-10-09 |
| Method of fabricating semiconductor devices using laser annealing Grant 4,415,383 - Naem , et al. November 15, 1 | 1983-11-15 |
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