Caimi; Carlo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Caimi; Carlo.The latest application filed is for "continuity test in electronic devices with multiple-connection leads".

Company Profile

0.6.7

Caimi; Carlo - Cinisello Balsamo IT
Caimi; Carlo - I-20092 Cinisello Balsamo MI
Caimi; Carlo - Cinisello Balsamo MI

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Continuity test in electronic devices with multiple-connection leads Grant 9,176,191 - Rossi , et al. November 3, 2	2015-11-03
Solar light concentration photovoltaic conversion system using a wavelength splitter and lambda-specific photovoltaic cells optically coupled to lambda-dedicated fibers illuminated by respective split beams Grant 9,136,416 - Caimi , et al. September 15, 2	2015-09-15
Continuity Test In Electronic Devices With Multiple-connection Leads App 20130335107 - ROSSI; Giorgio ; et al.	2013-12-19
Solar Light Concentration Photovoltaic Conversion System Using A Wavelength Splitter And Lambda-specific Photovoltaic Cells Optically Coupled To Lambda-dedicated Fibers Illuminated By Respective Split Beams App 20130146121 - CAIMI; Carlo ; et al.	2013-06-13
Electronic memory device having high integration density non-volatile memory cells and a reduced capacitive coupling Grant 7,593,247 - Khouri , et al. September 22, 2	2009-09-22
Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell Grant 7,319,604 - Khouri , et al. January 15, 2	2008-01-15
MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact App 20060246646 - Caimi; Carlo ; et al.	2006-11-02
MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact Grant 7,091,570 - Caimi , et al. August 15, 2	2006-08-15
Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell App 20060158931 - Khouri; Osama ; et al.	2006-07-20
Electronic memory device having high integration density non-volatile memory cells and a reduced capacitive coupling App 20060158934 - Khouri; Osama ; et al.	2006-07-20
MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology Grant 7,023,047 - Tessa Contin , et al. April 4, 2	2006-04-04
MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact App 20050116288 - Caimi, Carlo ; et al.	2005-06-02
MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology App 20040188759 - Contin, Valentina Tessa ; et al.	2004-09-30

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.